CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:RISC-CPU

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-04-25
  • 文件大小：
    4.14mb
  • 已下载：
    0次
  • 提 供 者：
    刘***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

精简指令集 CPU 通过仿真验证正确

(使用之前务必看readme文件，和结构图!)

1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。

2. 学习时务必先搞明白框图原理，和数据流动！！！

3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。

4. 理解数据总线，和地址总线。区分数据和地址。

5. 仔细调试，因为书中有很多小错误。



程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

RISC-CPU/CPU/accum.v
RISC-CPU/CPU/accum.v.bak
RISC-CPU/CPU/adr.v
RISC-CPU/CPU/alu.v
RISC-CPU/CPU/alu.v.bak
RISC-CPU/CPU/clk_gen.v
RISC-CPU/CPU/clk_gen.v.bak
RISC-CPU/CPU/counter.v
RISC-CPU/CPU/CPU.asm.rpt
RISC-CPU/CPU/CPU.done
RISC-CPU/CPU/CPU.fit.rpt
RISC-CPU/CPU/CPU.fit.smsg
RISC-CPU/CPU/CPU.fit.summary
RISC-CPU/CPU/CPU.flow.rpt
RISC-CPU/CPU/CPU.map.rpt
RISC-CPU/CPU/CPU.map.summary
RISC-CPU/CPU/CPU.pin
RISC-CPU/CPU/CPU.qpf
RISC-CPU/CPU/CPU.qsf
RISC-CPU/CPU/CPU.sof
RISC-CPU/CPU/CPU.sta.rpt
RISC-CPU/CPU/CPU.sta.summary
RISC-CPU/CPU/datactl.v
RISC-CPU/CPU/datactl.v.bak
RISC-CPU/CPU/db/CPU.(0).cnf.cdb
RISC-CPU/CPU/db/CPU.(0).cnf.hdb
RISC-CPU/CPU/db/CPU.amm.cdb
RISC-CPU/CPU/db/CPU.asm.qmsg
RISC-CPU/CPU/db/CPU.asm.rdb
RISC-CPU/CPU/db/CPU.asm_labs.ddb
RISC-CPU/CPU/db/CPU.cbx.xml
RISC-CPU/CPU/db/CPU.cmp.bpm
RISC-CPU/CPU/db/CPU.cmp.cdb
RISC-CPU/CPU/db/CPU.cmp.hdb
RISC-CPU/CPU/db/CPU.cmp.kpt
RISC-CPU/CPU/db/CPU.cmp.logdb
RISC-CPU/CPU/db/CPU.cmp.rdb
RISC-CPU/CPU/db/CPU.cmp_merge.kpt
RISC-CPU/CPU/db/CPU.db_info
RISC-CPU/CPU/db/CPU.fit.qmsg
RISC-CPU/CPU/db/CPU.hier_info
RISC-CPU/CPU/db/CPU.hif
RISC-CPU/CPU/db/CPU.idb.cdb
RISC-CPU/CPU/db/CPU.lpc.html
RISC-CPU/CPU/db/CPU.lpc.rdb
RISC-CPU/CPU/db/CPU.lpc.txt
RISC-CPU/CPU/db/CPU.map.bpm
RISC-CPU/CPU/db/CPU.map.cdb
RISC-CPU/CPU/db/CPU.map.hdb
RISC-CPU/CPU/db/CPU.map.kpt
RISC-CPU/CPU/db/CPU.map.logdb
RISC-CPU/CPU/db/CPU.map.qmsg
RISC-CPU/CPU/db/CPU.map_bb.cdb
RISC-CPU/CPU/db/CPU.map_bb.hdb
RISC-CPU/CPU/db/CPU.map_bb.logdb
RISC-CPU/CPU/db/CPU.pre_map.cdb
RISC-CPU/CPU/db/CPU.pre_map.hdb
RISC-CPU/CPU/db/CPU.rtlv.hdb
RISC-CPU/CPU/db/CPU.rtlv_sg.cdb
RISC-CPU/CPU/db/CPU.rtlv_sg_swap.cdb
RISC-CPU/CPU/db/CPU.sgdiff.cdb
RISC-CPU/CPU/db/CPU.sgdiff.hdb
RISC-CPU/CPU/db/CPU.sld_design_entry.sci
RISC-CPU/CPU/db/CPU.sld_design_entry_dsc.sci
RISC-CPU/CPU/db/CPU.smart_action.txt
RISC-CPU/CPU/db/CPU.smp_dump.txt
RISC-CPU/CPU/db/CPU.sta.qmsg
RISC-CPU/CPU/db/CPU.sta.rdb
RISC-CPU/CPU/db/CPU.sta_cmp.7_slow_1200mv_85c.tdb
RISC-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
RISC-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
RISC-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
RISC-CPU/CPU/db/CPU.syn_hier_info
RISC-CPU/CPU/db/CPU.tiscmp.fastest_slow_1200mv_0c.ddb
RISC-CPU/CPU/db/CPU.tiscmp.fastest_slow_1200mv_85c.ddb
RISC-CPU/CPU/db/CPU.tiscmp.fast_1200mv_0c.ddb
RISC-CPU/CPU/db/CPU.tiscmp.slow_1200mv_0c.ddb
RISC-CPU/CPU/db/CPU.tiscmp.slow_1200mv_85c.ddb
RISC-CPU/CPU/db/CPU.tis_db_list.ddb
RISC-CPU/CPU/db/logic_util_heursitic.dat
RISC-CPU/CPU/db/prev_cmp_CPU.qmsg
RISC-CPU/CPU/db
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.db_info
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.cdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcfdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.cdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.cdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hb_info
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.sig
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hdb
RISC-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.kpt
RISC-CPU/CPU/incremental_db/compiled_partitions
RISC-CPU/CPU/incremental_db/README
RISC-CPU/CPU/incremental_db
RISC-CPU/CPU/machine.v
RISC-CPU/CPU/machine.v.bak
RISC-CPU/CPU/machinectl.v.bak
RISC-CPU/CPU/register.v
RISC-CPU/CPU/register.v.bak
RISC-CPU/CPU/rom_ram.v
RISC-CPU/CPU/rom_ram.v.bak
RISC-CPU/CPU
RISC-CPU/CPU_sim/accum.v
RISC-CPU/CPU_sim/addr_decode.v
RISC-CPU/CPU_sim/adr.v
RISC-CPU/CPU_sim/alu.v
RISC-CPU/CPU_sim/clk_gen.v
RISC-CPU/CPU_sim/counter.v
RISC-CPU/CPU_sim/CPU.cr.mti
RISC-CPU/CPU_sim/CPU.mpf
RISC-CPU/CPU_sim/cpu.v
RISC-CPU/CPU_sim/cpu.v.bak
RISC-CPU/CPU_sim/cputop.v
RISC-CPU/CPU_sim/cputop.v.bak
RISC-CPU/CPU_sim/datactl.v
RISC-CPU/CPU_sim/machine.v
RISC-CPU/CPU_sim/machine.v.bak
RISC-CPU/CPU_sim/machinectl.v
RISC-CPU/CPU_sim/my_state_test.v
RISC-CPU/CPU_sim/my_state_test.v.bak
RISC-CPU/CPU_sim/register.v
RISC-CPU/CPU_sim/rom_ram.v
RISC-CPU/CPU_sim/tcl_stacktrace.txt
RISC-CPU/CPU_sim/test1.dat
RISC-CPU/CPU_sim/test1.pro
RISC-CPU/CPU_sim/test2.dat
RISC-CPU/CPU_sim/test2.pro
RISC-CPU/CPU_sim/test3.dat
RISC-CPU/CPU_sim/test3.pro
RISC-CPU/CPU_sim/test_data/test1.dat
RISC-CPU/CPU_sim/test_data/test1.pro
RISC-CPU/CPU_sim/test_data
RISC-CPU/CPU_sim/transcript
RISC-CPU/CPU_sim/vish_stacktrace.vstf
RISC-CPU/CPU_sim/vsim.wlf
RISC-CPU/CPU_sim/work/@_opt/vopt0rsnds
RISC-CPU/CPU_sim/work/@_opt/vopt19vrcs
RISC-CPU/CPU_sim/work/@_opt/vopt1arvvt
RISC-CPU/CPU_sim/work/@_opt/vo

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com