文件名称:madadianji_controller
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- 上传时间:2013-05-03
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文件大小:322.67kb
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使用altera MAX II CPLD 做的马达步进电机控制器。-Motor stepper motor controller using the altera MAX II CPLD to do.
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下载文件列表
madadianji_controller/an488_design_example/code/stepmot.v
madadianji_controller/an488_design_example/modelsim/stepmot.v
madadianji_controller/an488_design_example/modelsim/stepmot_sim.cr.mti
madadianji_controller/an488_design_example/modelsim/stepmot_sim.mpf
madadianji_controller/an488_design_example/modelsim/test_stepmot.v
madadianji_controller/an488_design_example/modelsim/transcript
madadianji_controller/an488_design_example/modelsim/wave.bmp
madadianji_controller/an488_design_example/modelsim/wave.do
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/divider/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/divider/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/divider/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/divider1/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/divider1/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/divider1/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_io/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_io/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_io/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_nmux21/verilog.psm
madadianji_controller/an488_des
madadianji_controller/an488_design_example/modelsim/stepmot.v
madadianji_controller/an488_design_example/modelsim/stepmot_sim.cr.mti
madadianji_controller/an488_design_example/modelsim/stepmot_sim.mpf
madadianji_controller/an488_design_example/modelsim/test_stepmot.v
madadianji_controller/an488_design_example/modelsim/transcript
madadianji_controller/an488_design_example/modelsim/wave.bmp
madadianji_controller/an488_design_example/modelsim/wave.do
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/@m@a@x@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/divider/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/divider/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/divider/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/divider1/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/divider1/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/divider1/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_and1/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_and16/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_asynch_lcell/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_b17mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_b5mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_bmux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_crcblock/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_dffe/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_io/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_io/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_io/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_jtag/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_latch/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_lcell_register/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_mux21/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/verilog.psm
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/_primary.dat
madadianji_controller/an488_design_example/modelsim/work/maxii_mux41/_primary.vhd
madadianji_controller/an488_design_example/modelsim/work/maxii_nmux21/verilog.psm
madadianji_controller/an488_des
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