文件名称:clock-generator
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- 上传时间:2013-05-15
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文件大小:121kb
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在集成电路设计中,时钟乃必备元素,但时钟产生器一般为模拟或者数模混合电路,在以数字电路为主的ASIC设计中,一般使用其模型来仿真。
写一个时钟产生器模块。-In integrated circuit design, the clock is an essential element, but the clock generator is generally analog or mixed analog-digital circuits, digital circuits based ASIC design, the general use of the model to emulate. Write a clock generator module.
写一个时钟产生器模块。-In integrated circuit design, the clock is an essential element, but the clock generator is generally analog or mixed analog-digital circuits, digital circuits based ASIC design, the general use of the model to emulate. Write a clock generator module.
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下载文件列表
clk_counter.v
clk_tb.v
Homework 2.doc
clk_tb.v
Homework 2.doc
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