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文件名称:Midian_fpga

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  • 上传时间:
    2013-05-31
  • 文件大小:
    8.48mb
  • 已下载:
    2次
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介绍说明--下载内容来自于网络,使用问题请自行百度

图像处理中用到的中值滤波,FPGA实现。verilog语言。-Used in image processing median filter, FPGA implementation. verilog language.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Midian_fpga/
Midian_fpga/zhongzhilvbo/
Midian_fpga/zhongzhilvbo/compare8.asy
Midian_fpga/zhongzhilvbo/compare8.v
Midian_fpga/zhongzhilvbo/compare8.veo
Midian_fpga/zhongzhilvbo/compare8.vhd
Midian_fpga/zhongzhilvbo/compare8.vho
Midian_fpga/zhongzhilvbo/compare8.xco
Midian_fpga/zhongzhilvbo/compare8_c_compare_v9_0_xst_1.ngc_xst.xrpt
Midian_fpga/zhongzhilvbo/compare8_flist.txt
Midian_fpga/zhongzhilvbo/compare8_readme.txt
Midian_fpga/zhongzhilvbo/coregen.log
Midian_fpga/zhongzhilvbo/din1tt.dat
Midian_fpga/zhongzhilvbo/din2tt.dat
Midian_fpga/zhongzhilvbo/din3tt.dat
Midian_fpga/zhongzhilvbo/din4tt.dat
Midian_fpga/zhongzhilvbo/din5tt.dat
Midian_fpga/zhongzhilvbo/din6tt.dat
Midian_fpga/zhongzhilvbo/din7tt.dat
Midian_fpga/zhongzhilvbo/din8tt.dat
Midian_fpga/zhongzhilvbo/din9tt.dat
Midian_fpga/zhongzhilvbo/dual_ram.asy
Midian_fpga/zhongzhilvbo/dual_ram.v
Midian_fpga/zhongzhilvbo/dual_ram.veo
Midian_fpga/zhongzhilvbo/dual_ram.vhd
Midian_fpga/zhongzhilvbo/dual_ram.vho
Midian_fpga/zhongzhilvbo/dual_ram.xco
Midian_fpga/zhongzhilvbo/dual_ram_blk_mem_gen_v2_8_xst_1.ngc_xst.xrpt
Midian_fpga/zhongzhilvbo/dual_ram_flist.txt
Midian_fpga/zhongzhilvbo/dual_ram_readme.txt
Midian_fpga/zhongzhilvbo/fpga_dout.txt
Midian_fpga/zhongzhilvbo/fuse.log
Midian_fpga/zhongzhilvbo/ipcore_dir/
Midian_fpga/zhongzhilvbo/iseconfig/
Midian_fpga/zhongzhilvbo/iseconfig/zhongzhilvbo.projectmgr
Midian_fpga/zhongzhilvbo/iseconfig/zhongzhilvbo.xreport
Midian_fpga/zhongzhilvbo/isim.cmd
Midian_fpga/zhongzhilvbo/isim.hdlsourcefiles
Midian_fpga/zhongzhilvbo/isim.log
Midian_fpga/zhongzhilvbo/isimwavedata.xwv
Midian_fpga/zhongzhilvbo/median.v
Midian_fpga/zhongzhilvbo/median_xst.xrpt
Midian_fpga/zhongzhilvbo/modelsim.ini
Midian_fpga/zhongzhilvbo/s2p.v
Midian_fpga/zhongzhilvbo/tb_compare8.v
Midian_fpga/zhongzhilvbo/tb_compare8_isim_beh.wfs
Midian_fpga/zhongzhilvbo/tb_compare8_wave.fdo
Midian_fpga/zhongzhilvbo/tb_midfilt2_demo.fdo
Midian_fpga/zhongzhilvbo/tb_midfilt2_demo.udo
Midian_fpga/zhongzhilvbo/tb_midfilt2_demo.v
Midian_fpga/zhongzhilvbo/tb_midfilt2_demo_isim_beh.exe
Midian_fpga/zhongzhilvbo/tb_midfilt2_demo_wave.fdo
Midian_fpga/zhongzhilvbo/tb_zhongzhilvbo.fdo
Midian_fpga/zhongzhilvbo/tb_zhongzhilvbo.udo
Midian_fpga/zhongzhilvbo/tb_zhongzhilvbo.v
Midian_fpga/zhongzhilvbo/tb_zhongzhilvbo_wave.fdo
Midian_fpga/zhongzhilvbo/top_summary.html
Midian_fpga/zhongzhilvbo/top_xst.xrpt
Midian_fpga/zhongzhilvbo/transcript
Midian_fpga/zhongzhilvbo/uutcompare8.v
Midian_fpga/zhongzhilvbo/uutcompare8_summary.html
Midian_fpga/zhongzhilvbo/uutcompare8_xst.xrpt
Midian_fpga/zhongzhilvbo/vsim.wlf
Midian_fpga/zhongzhilvbo/webtalk_pn.xml
Midian_fpga/zhongzhilvbo/wlftjf5727
Midian_fpga/zhongzhilvbo/wlftsg9c32
Midian_fpga/zhongzhilvbo/wlftxcad2g
Midian_fpga/zhongzhilvbo/wlftznqhnr
Midian_fpga/zhongzhilvbo/work/
Midian_fpga/zhongzhilvbo/work/@_opt/
Midian_fpga/zhongzhilvbo/work/@_opt1/
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt03q516
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt11ni3h
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt1yyc2b
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt2wxs4n
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt2zkz5w
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt3q516v
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt3tw671
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt4m4e86
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt4rvj9c
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt5j3vah
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt5nt0cq
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt6eb2cn
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt6h28dw
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt7cafe1
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt7f1mf7
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt8a9wgc
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt8d02ii
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt95h3ih
Midian_fpga/zhongzhilvbo/work/@_opt1/vopt9889jq
Midian_fpga/zhongzhilvbo/work/@_opt1/vopta3ggkw
Midian_fpga/zhongzhilvbo/work/@_opt1/vopta67nm2
Midian_fpga/zhongzhilvbo/work/@_opt1/voptb1fxn7
Midian_fpga/zhongzhilvbo/work/@_opt1/voptb463rd
Midian_fpga/zhongzhilvbo/work/@_opt1/voptcwn4rc
Midian_fpga/zhongzhilvbo/work/@_opt1/voptczdasi
Midian_fpga/zhongzhilvbo/work/@_opt1/voptdtmhtq
Midian_fpga/zhongzhilvbo/work/@_opt1/voptdxcqvx
Midian_fpga/zhongzhilvbo/work/@_opt1/vopterkyw2
Midian_fpga/zhongzhilvbo/work/@_opt1/voptevb4y8
Midian_fpga/zhongzhilvbo/work/@_opt1/voptfjw5y7
Midian_fpga/zhongzhilvbo/work/@_opt1/voptfnjbzd
Midian_fpga/zhongzhilvbo/work/@_opt1/voptghvi0j
Midian_fpga/zhongzhilvbo/work/@_opt1/voptgkir1s
Midian_fpga/zhongzhilvbo/work/@_opt1/vopthftz2y
Midian_fpga/zhongzhilvbo/work/@_opt1/vopthih544
Midian_fpga/zhongzhilvbo/work/@_opt1/voptia2743
Midian_fpga/zhongzhilvbo/work/@_opt1/voptidsc59
Midian_fpga/zhongzhilvbo/work/@_opt1/voptj81k6e
Midian_fpga/zhongzhilvbo/work/@_opt1/voptjbrs7k
Midian_fpga/zhongzhilvbo/work/@_opt1/voptk6019s
Midian_fpga/zhongzhilvbo/work/@_opt1/voptm188ay
Midian_fpga/zhongzhilvbo/work/@_opt1/voptm4zdb4
Midian_fpga/zhongzhilvbo/work/@_opt1/voptn2ytdf
Midian_fpga/zhongzhilvbo/work/@_opt1/voptnz6mc9
Midian_fpga/zhongzhilvbo/work/@_opt1/voptqx52fk
Midian_fpga/zhongzhilvbo/work/@_opt1/voptrrd9gs
Midian_fpga/zhongzhilvbo/work/@_opt1/voptrv4fhz
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