library ieee

use ieee.std_logic_1164.all

entity decoder is

port (clk:in std_logic

clr:in std_logic

data_in:in std_logic --待解码信元输入端；

data_out:out std_logic) --解码信元输出端；

end decoder

architecture behave of decoder is

component dff2 --上升沿D 触发器；

port(d,clk,clr:in std_logic

q:out std_logic)

end component

component xor2 --两输入异或门；

port (a,b:in std_logic

y:out std_logic)

end component

--一输入两输出电子开关；

component switch21

port (clk,d,clr:in std_logic

y:out std_logic)

end component

component emendation --校正电路；

port (d,clk,clr:in std_logic

y:out std_logic)

end component

signal s1,s2,s3,s4,s5: std_logic

begin

u0:switch21 port map (data_in ,clk,clr,s1,s2)

u1: emendation port map (s1,clk,clr,s3)

u2: dff2 port map (s2,clk,clr,s4)

u3: xor2 port map (s3,s4,s5)

data_out <= s5

end -library ieee　use ieee.std_logic_1164.all　entity decoder is port (clk: in std_logic　clr: in std_logic　data_in: in std_logic - be decoded cell inputs　data_out: out std_logic) - Decoding Cell output　end decoder　architecture behave of decoder is component dff2- edge D flip-flop　port (d, clk, clr: in std_logic　q: out std_logic)　end component　component xor2- two input XOR gate　 port (a, b: in std_logic　y: out std_logic)　end component - an input two output electronic switch　component switch21 port (clk, d, clr: in std_logic　y: out std_logic)　end component　component emendation- correction circuit　port (d, clk, clr: in std_logic　y: out std_logic)　end component　signal s1, s2, s3, s4, s5: std_logic　begin u0: switch21 port map (data_in, clk , clr, s1, s2)　u1: emendation port map (s1, clk, clr, s3)　u2: dff2 port map (s2, clk, clr, s4)　u3: xor2 port map (s3, s4, s5)　 data_out < = s5　end