sim/
sim/memfile.dat
sim/memfile2.dat
sim/mips.v
sim/mips.v.bak
sim/sim.cr.mti
sim/sim.mpf
sim/transcript
sim/vsim.wlf
sim/work/
sim/work/_info
sim/work/alu/
sim/work/alu/_primary.dat
sim/work/alu/_primary.vhd
sim/work/alu/verilog.asm
sim/work/alucontrol/
sim/work/alucontrol/_primary.dat
sim/work/alucontrol/_primary.vhd
sim/work/alucontrol/verilog.asm
sim/work/controller/
sim/work/controller/_primary.dat
sim/work/controller/_primary.vhd
sim/work/controller/verilog.asm
sim/work/datapath/
sim/work/datapath/_primary.dat
sim/work/datapath/_primary.vhd
sim/work/datapath/verilog.asm
sim/work/exmemory/
sim/work/exmemory/_primary.dat
sim/work/exmemory/_primary.vhd
sim/work/exmemory/verilog.asm
sim/work/flop/
sim/work/flop/_primary.dat
sim/work/flop/_primary.vhd
sim/work/flop/verilog.asm
sim/work/flopen/
sim/work/flopen/_primary.dat
sim/work/flopen/_primary.vhd
sim/work/flopen/verilog.asm
sim/work/flopenr/
sim/work/flopenr/_primary.dat
sim/work/flopenr/_primary.vhd
sim/work/flopenr/verilog.asm
sim/work/mips/
sim/work/mips/_primary.dat
sim/work/mips/_primary.vhd
sim/work/mips/verilog.asm
sim/work/mux2/
sim/work/mux2/_primary.dat
sim/work/mux2/_primary.vhd
sim/work/mux2/verilog.asm
sim/work/mux4/
sim/work/mux4/_primary.dat
sim/work/mux4/_primary.vhd
sim/work/mux4/verilog.asm
sim/work/regfile/
sim/work/regfile/_primary.dat
sim/work/regfile/_primary.vhd
sim/work/regfile/verilog.asm
sim/work/top/
sim/work/top/_primary.dat
sim/work/top/_primary.vhd
sim/work/top/verilog.asm
sim/work/zerodetect/
sim/work/zerodetect/_primary.dat
sim/work/zerodetect/_primary.vhd
sim/work/zerodetect/verilog.asm
sim/新建文本文档.txt