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文件名称:Digital-clock

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-08-27
  • 文件大小：
    3.65mb
  • 已下载：
    0次
  • 提 供 者：
    z*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

本程序是用QUARTUS软件设计的数字钟，采用verilog语言描述-This procedure is to use the QUARTUS software design of digital clock, using verilog language descr iption


(系统自动生成,下载前可以参看下载内容)

下载文件列表

Digital clock/
Digital clock/count_24.v
Digital clock/count_24.v.bak
Digital clock/count_60.v
Digital clock/count_60.v.bak
Digital clock/db/
Digital clock/db/digit_clock.(0).cnf.cdb
Digital clock/db/digit_clock.(0).cnf.hdb
Digital clock/db/digit_clock.(1).cnf.cdb
Digital clock/db/digit_clock.(1).cnf.hdb
Digital clock/db/digit_clock.(2).cnf.cdb
Digital clock/db/digit_clock.(2).cnf.hdb
Digital clock/db/digit_clock.asm.qmsg
Digital clock/db/digit_clock.asm.rdb
Digital clock/db/digit_clock.cbx.xml
Digital clock/db/digit_clock.cmp.bpm
Digital clock/db/digit_clock.cmp.cdb
Digital clock/db/digit_clock.cmp.ecobp
Digital clock/db/digit_clock.cmp.hdb
Digital clock/db/digit_clock.cmp.kpt
Digital clock/db/digit_clock.cmp.logdb
Digital clock/db/digit_clock.cmp.rdb
Digital clock/db/digit_clock.cmp.tdb
Digital clock/db/digit_clock.cmp0.ddb
Digital clock/db/digit_clock.cmp_merge.kpt
Digital clock/db/digit_clock.db_info
Digital clock/db/digit_clock.eco.cdb
Digital clock/db/digit_clock.eda.qmsg
Digital clock/db/digit_clock.eds_overflow
Digital clock/db/digit_clock.fit.qmsg
Digital clock/db/digit_clock.hier_info
Digital clock/db/digit_clock.hif
Digital clock/db/digit_clock.lpc.html
Digital clock/db/digit_clock.lpc.rdb
Digital clock/db/digit_clock.lpc.txt
Digital clock/db/digit_clock.map.bpm
Digital clock/db/digit_clock.map.cdb
Digital clock/db/digit_clock.map.ecobp
Digital clock/db/digit_clock.map.hdb
Digital clock/db/digit_clock.map.kpt
Digital clock/db/digit_clock.map.logdb
Digital clock/db/digit_clock.map.qmsg
Digital clock/db/digit_clock.map_bb.cdb
Digital clock/db/digit_clock.map_bb.hdb
Digital clock/db/digit_clock.map_bb.logdb
Digital clock/db/digit_clock.pre_map.cdb
Digital clock/db/digit_clock.pre_map.hdb
Digital clock/db/digit_clock.rtlv.hdb
Digital clock/db/digit_clock.rtlv_sg.cdb
Digital clock/db/digit_clock.rtlv_sg_swap.cdb
Digital clock/db/digit_clock.sgdiff.cdb
Digital clock/db/digit_clock.sgdiff.hdb
Digital clock/db/digit_clock.sim.cvwf
Digital clock/db/digit_clock.sim.hdb
Digital clock/db/digit_clock.sim.qmsg
Digital clock/db/digit_clock.sim.rdb
Digital clock/db/digit_clock.sld_design_entry.sci
Digital clock/db/digit_clock.sld_design_entry_dsc.sci
Digital clock/db/digit_clock.smart_action.txt
Digital clock/db/digit_clock.syn_hier_info
Digital clock/db/digit_clock.tan.qmsg
Digital clock/db/digit_clock.tis_db_list.ddb
Digital clock/db/digit_clock.tmw_info
Digital clock/db/logic_util_heursitic.dat
Digital clock/db/prev_cmp_digit_clock.asm.qmsg
Digital clock/db/prev_cmp_digit_clock.eda.qmsg
Digital clock/db/prev_cmp_digit_clock.fit.qmsg
Digital clock/db/prev_cmp_digit_clock.map.qmsg
Digital clock/db/prev_cmp_digit_clock.qmsg
Digital clock/db/prev_cmp_digit_clock.sim.qmsg
Digital clock/db/prev_cmp_digit_clock.tan.qmsg
Digital clock/db/wed.wsf
Digital clock/digit_clock.asm.rpt
Digital clock/digit_clock.done
Digital clock/digit_clock.dpf
Digital clock/digit_clock.eda.rpt
Digital clock/digit_clock.fit.rpt
Digital clock/digit_clock.fit.smsg
Digital clock/digit_clock.fit.summary
Digital clock/digit_clock.flow.rpt
Digital clock/digit_clock.map.rpt
Digital clock/digit_clock.map.summary
Digital clock/digit_clock.pin
Digital clock/digit_clock.pof
Digital clock/digit_clock.qpf
Digital clock/digit_clock.qsf
Digital clock/digit_clock.qws
Digital clock/digit_clock.sim.rpt
Digital clock/digit_clock.sof
Digital clock/digit_clock.tan.rpt
Digital clock/digit_clock.tan.summary
Digital clock/digit_clock.v
Digital clock/digit_clock.v.bak
Digital clock/digit_clock.vwf
Digital clock/digit_clock_nativelink_simulation.rpt
Digital clock/incremental_db/
Digital clock/incremental_db/compiled_partitions/
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.cdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.dfp
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.hdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.kpt
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.logdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.rcfdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.cmp.re.rcfdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.map.cdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.map.dpi
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.map.hdb
Digital clock/incremental_db/compiled_partitions/digit_clock.root_partition.map.kpt
Digital clock/incremental_db/README
Digital clock/simulation/
Digital clock/simulation/modelsim/
Digital clock/simulation/modelsim/digit_clock.sft
Digital clock/simulation/modelsim/digit_clock.vo
Digital clock/simulation/modelsim/digit_clock.vt
Digital clock/simulation/modelsim/digit_clock.vt.bak
Digital clock/simulation/modelsim/digit_clock_modelsim.xrf
Digital clock/simulation/modelsim/digit_clock_run_msim_rtl_verilog.do
Digital clock/simulation/modelsim/digit_clock_run_msim_rtl_verilog.do.bak
Digital clock/simulation/modelsim/digit_clock_v.sd

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