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文件名称:asynram

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
  • 上传时间：
    2013-09-05
  • 文件大小：
    330.56kb
  • 已下载：
    0次
  • 提 供 者：
    Bi***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

设计32×6位的RAM，其结构图如图2所示。其中，adr为地址引脚，cs、wr、rd分别为片

选、写和读引脚，din_out为输入输出引脚。当cs=0且wr由低到高（上升沿）时，din上的输

入数据写入adr指示的单元中；当cs=0且rd=0时，adr对应单元的数据在dout数据线上读出。

因wr在上升沿时写入数据，因此可以采用TEC-CA平台上的单脉冲按钮作为wr。-Design 326 of RAM, the structure shown in Figure 2. Which, adr as address pins, cs, wr, rd, respectively, for the chip select, write and read the pin, din_out to input or output pin. When cs = 0 and wr from low to high (rising) when, din input data is written on the instructions of the unit adr　when cs = 0 and rd = 0 时, adr corresponding data element in the data line read dout out. Because when data is written on the rising edge wr, so you can use TEC-CA single pulse button on the platform as a wr.
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下载文件列表

asynram/asynram.asm.rpt
asynram/asynram.cdf
asynram/asynram.done
asynram/asynram.fit.eqn
asynram/asynram.fit.rpt
asynram/asynram.fit.summary
asynram/asynram.flow.rpt
asynram/asynram.map.eqn
asynram/asynram.map.rpt
asynram/asynram.map.summary
asynram/asynram.pin
asynram/asynram.pof
asynram/asynram.qpf
asynram/asynram.qsf
asynram/asynram.qws
asynram/asynram.sof
asynram/asynram.tan.rpt
asynram/asynram.tan.summary
asynram/asynram.vhd
asynram/cmp_state.ini
asynram/db/asynram.(0).cnf.cdb
asynram/db/asynram.(0).cnf.hdb
asynram/db/asynram.asm.qmsg
asynram/db/asynram.cbx.xml
asynram/db/asynram.cmp.cdb
asynram/db/asynram.cmp.hdb
asynram/db/asynram.cmp.rdb
asynram/db/asynram.cmp.tdb
asynram/db/asynram.cmp0.ddb
asynram/db/asynram.db_info
asynram/db/asynram.eco.cdb
asynram/db/asynram.fit.qmsg
asynram/db/asynram.hier_info
asynram/db/asynram.hif
asynram/db/asynram.map.cdb
asynram/db/asynram.map.hdb
asynram/db/asynram.map.qmsg
asynram/db/asynram.pre_map.cdb
asynram/db/asynram.pre_map.hdb
asynram/db/asynram.psp
asynram/db/asynram.rtlv.hdb
asynram/db/asynram.rtlv_sg.cdb
asynram/db/asynram.rtlv_sg_swap.cdb
asynram/db/asynram.sgdiff.cdb
asynram/db/asynram.sgdiff.hdb
asynram/db/asynram.signalprobe.cdb
asynram/db/asynram.sld_design_entry.sci
asynram/db/asynram.sld_design_entry_dsc.sci
asynram/db/asynram.syn_hier_info
asynram/db/asynram.tan.qmsg
asynram/db/asynram_cmp.qrpt
asynram/db
asynram

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