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文件名称:zuoye2

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [PDF]
  • 上传时间：
    2013-09-18
  • 文件大小：
    3.56mb
  • 已下载：
    0次
  • 提 供 者：
    林***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

主要编写了一组二进制数据通过根升余弦滤波器后的波形，但并没有使用ISE内部的FIR滤波器内核，该程序相当于编写了一个根升余弦滤波器。-Mainly prepared a set of binary data through the root raised cosine filter waveform after, but did not use the ISE internal FIR filter kernel, the program is equivalent to the preparation of a root raised cosine filter.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

zuoye2/ipcore_dir/coregen.cgp
zuoye2/ipcore_dir/coregen.log
zuoye2/ipcore_dir/create_rcosfir_ROM.tcl
zuoye2/ipcore_dir/create_ROM_sig.tcl
zuoye2/ipcore_dir/edit_rcosfir_ROM.tcl
zuoye2/ipcore_dir/edit_ROM_sig.tcl
zuoye2/ipcore_dir/rcosfir_ROM/blk_mem_gen_v7_2_readme.txt
zuoye2/ipcore_dir/rcosfir_ROM/doc/blk_mem_gen_v7_2_vinfo.html
zuoye2/ipcore_dir/rcosfir_ROM/doc/pg058-blk-mem-gen.pdf
zuoye2/ipcore_dir/rcosfir_ROM/example_design/rcosfir_ROM_exdes.ucf
zuoye2/ipcore_dir/rcosfir_ROM/example_design/rcosfir_ROM_exdes.vhd
zuoye2/ipcore_dir/rcosfir_ROM/example_design/rcosfir_ROM_exdes.xdc
zuoye2/ipcore_dir/rcosfir_ROM/example_design/rcosfir_ROM_prod.vhd
zuoye2/ipcore_dir/rcosfir_ROM/implement/implement.bat
zuoye2/ipcore_dir/rcosfir_ROM/implement/implement.sh
zuoye2/ipcore_dir/rcosfir_ROM/implement/planAhead_ise.bat
zuoye2/ipcore_dir/rcosfir_ROM/implement/planAhead_ise.sh
zuoye2/ipcore_dir/rcosfir_ROM/implement/planAhead_ise.tcl
zuoye2/ipcore_dir/rcosfir_ROM/implement/xst.prj
zuoye2/ipcore_dir/rcosfir_ROM/implement/xst.scr
zuoye2/ipcore_dir/rcosfir_ROM/simulation/addr_gen.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/bmg_stim_gen.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/bmg_tb_pkg.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simcmds.tcl
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_isim.bat
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_mti.bat
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_mti.do
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_mti.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_ncsim.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/simulate_vcs.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/ucli_commands.key
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/vcs_session.tcl
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/wave_mti.do
zuoye2/ipcore_dir/rcosfir_ROM/simulation/functional/wave_ncsim.sv
zuoye2/ipcore_dir/rcosfir_ROM/simulation/random.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/rcosfir_ROM_synth.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/rcosfir_ROM_tb.vhd
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simcmds.tcl
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_isim.bat
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_mti.bat
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_mti.do
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_mti.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_ncsim.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/simulate_vcs.sh
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/ucli_commands.key
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/vcs_session.tcl
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/wave_mti.do
zuoye2/ipcore_dir/rcosfir_ROM/simulation/timing/wave_ncsim.sv
zuoye2/ipcore_dir/rcosfir_ROM.asy
zuoye2/ipcore_dir/rcosfir_ROM.gise
zuoye2/ipcore_dir/rcosfir_ROM.mif
zuoye2/ipcore_dir/rcosfir_ROM.ncf
zuoye2/ipcore_dir/rcosfir_ROM.ngc
zuoye2/ipcore_dir/rcosfir_ROM.sym
zuoye2/ipcore_dir/rcosfir_ROM.v
zuoye2/ipcore_dir/rcosfir_ROM.veo
zuoye2/ipcore_dir/rcosfir_ROM.xco
zuoye2/ipcore_dir/rcosfir_ROM.xise
zuoye2/ipcore_dir/rcosfir_ROM_flist.txt
zuoye2/ipcore_dir/rcosfir_ROM_synth.v
zuoye2/ipcore_dir/rcosfir_ROM_xmdf.tcl
zuoye2/ipcore_dir/ROM_sig/blk_mem_gen_v7_2_readme.txt
zuoye2/ipcore_dir/ROM_sig/doc/blk_mem_gen_v7_2_vinfo.html
zuoye2/ipcore_dir/ROM_sig/doc/pg058-blk-mem-gen.pdf
zuoye2/ipcore_dir/ROM_sig/example_design/ROM_sig_exdes.ucf
zuoye2/ipcore_dir/ROM_sig/example_design/ROM_sig_exdes.vhd
zuoye2/ipcore_dir/ROM_sig/example_design/ROM_sig_exdes.xdc
zuoye2/ipcore_dir/ROM_sig/example_design/ROM_sig_prod.vhd
zuoye2/ipcore_dir/ROM_sig/implement/implement.bat
zuoye2/ipcore_dir/ROM_sig/implement/implement.sh
zuoye2/ipcore_dir/ROM_sig/implement/planAhead_ise.bat
zuoye2/ipcore_dir/ROM_sig/implement/planAhead_ise.sh
zuoye2/ipcore_dir/ROM_sig/implement/planAhead_ise.tcl
zuoye2/ipcore_dir/ROM_sig/implement/xst.prj
zuoye2/ipcore_dir/ROM_sig/implement/xst.scr
zuoye2/ipcore_dir/ROM_sig/simulation/addr_gen.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/bmg_stim_gen.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/bmg_tb_pkg.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simcmds.tcl
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_isim.bat
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_mti.bat
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_mti.do
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_mti.sh
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_ncsim.sh
zuoye2/ipcore_dir/ROM_sig/simulation/functional/simulate_vcs.sh
zuoye2/ipcore_dir/ROM_sig/simulation/functional/ucli_commands.key
zuoye2/ipcore_dir/ROM_sig/simulation/functional/vcs_session.tcl
zuoye2/ipcore_dir/ROM_sig/simulation/functional/wave_mti.do
zuoye2/ipcore_dir/ROM_sig/simulation/functional/wave_ncsim.sv
zuoye2/ipcore_dir/ROM_sig/simulation/random.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/ROM_sig_synth.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/ROM_sig_tb.vhd
zuoye2/ipcore_dir/ROM_sig/simulation/timing/simcmds.tcl
zuoye2/ipcore_dir/ROM_sig/si

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