文件名称:sd_card_controller_latest.tar
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The SD Card Controller IP Core is MMC/SD communication controller designed to be
used in a System-on-Chip. The IP core provides a simple interface for CPU. The communication between the MMC/SD card controller and MMC/SD card is performed
according to the MMC/SD protocol.
used in a System-on-Chip. The IP core provides a simple interface for CPU. The communication between the MMC/SD card controller and MMC/SD card is performed
according to the MMC/SD protocol.
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下载文件列表
sd_card_controller/
sd_card_controller/tags/
sd_card_controller/branches/
sd_card_controller/trunk/
sd_card_controller/trunk/doc/
sd_card_controller/trunk/doc/bin/
sd_card_controller/trunk/doc/bin/ip_core.png
sd_card_controller/trunk/doc/bin/events.png
sd_card_controller/trunk/doc/bin/ip_core_if.png
sd_card_controller/trunk/doc/Wishbone SD Card Controller IP Specification.pdf
sd_card_controller/trunk/doc/references/
sd_card_controller/trunk/doc/references/part1_410.pdf
sd_card_controller/trunk/doc/src/
sd_card_controller/trunk/doc/src/events.odg
sd_card_controller/trunk/doc/src/usage.tex
sd_card_controller/trunk/doc/src/sw_if.tex
sd_card_controller/trunk/doc/src/introduction.tex
sd_card_controller/trunk/doc/src/specification.tex
sd_card_controller/trunk/doc/src/.gitignore
sd_card_controller/trunk/doc/src/ip_core_if.odg
sd_card_controller/trunk/doc/src/hdl_if.tex
sd_card_controller/trunk/doc/src/Makefile
sd_card_controller/trunk/doc/src/ip_core.odg
sd_card_controller/trunk/sim/
sd_card_controller/trunk/sim/rtl_sim/
sd_card_controller/trunk/sim/rtl_sim/run/
sd_card_controller/trunk/sim/rtl_sim/run/Makefile
sd_card_controller/trunk/sim/rtl_sim/bin/
sd_card_controller/trunk/sim/rtl_sim/bin/gui_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/ramdisk2.hex
sd_card_controller/trunk/sim/rtl_sim/bin/vcd_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/cli_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/wb_memory.txt
sd_card_controller/trunk/sim/rtl_sim/bin/FLASH.txt
sd_card_controller/trunk/sim/rtl_sim/bin/Makefile
sd_card_controller/trunk/README.md
sd_card_controller/trunk/bench/
sd_card_controller/trunk/bench/verilog/
sd_card_controller/trunk/bench/verilog/sd_cmd_serial_host_tb.sv
sd_card_controller/trunk/bench/verilog/sd_data_xfer_trig_tb.sv
sd_card_controller/trunk/bench/verilog/sd_controller_top_tb.sv
sd_card_controller/trunk/bench/verilog/edge_detect_tb.sv
sd_card_controller/trunk/bench/verilog/wb_slave_behavioral.v
sd_card_controller/trunk/bench/verilog/wb_bus_mon.v
sd_card_controller/trunk/bench/verilog/monostable_domain_cross_tb.sv
sd_card_controller/trunk/bench/verilog/wb_master32.v
sd_card_controller/trunk/bench/verilog/sd_data_master_tb.sv
sd_card_controller/trunk/bench/verilog/wb_master_behavioral.v
sd_card_controller/trunk/bench/verilog/sd_data_serial_host_tb.sv
sd_card_controller/trunk/bench/verilog/wb_model_defines.h
sd_card_controller/trunk/bench/verilog/bistable_domain_cross_tb.sv
sd_card_controller/trunk/bench/verilog/sd_cmd_master_tb.sv
sd_card_controller/trunk/bench/verilog/sd_fifo_filler_tb.sv
sd_card_controller/trunk/bench/verilog/sdModel.v
sd_card_controller/trunk/bench/verilog/sd_controller_wb_tb.sv
sd_card_controller/trunk/syn/
sd_card_controller/trunk/syn/quartus/
sd_card_controller/trunk/syn/quartus/run/
sd_card_controller/trunk/syn/quartus/run/Makefile
sd_card_controller/trunk/syn/quartus/bin/
sd_card_controller/trunk/syn/quartus/bin/pin_assignments.tcl
sd_card_controller/trunk/syn/quartus/bin/constraints.sdc
sd_card_controller/trunk/syn/quartus/bin/Makefile
sd_card_controller/trunk/syn/quartus/src/
sd_card_controller/trunk/syn/quartus/src/sdc_controller_top.v
sd_card_controller/trunk/rtl/
sd_card_controller/trunk/rtl/verilog/
sd_card_controller/trunk/rtl/verilog/sd_controller_wb.v
sd_card_controller/trunk/rtl/verilog/sd_data_serial_host.v
sd_card_controller/trunk/rtl/verilog/sd_crc_7.v
sd_card_controller/trunk/rtl/verilog/sd_cmd_master.v
sd_card_controller/trunk/rtl/verilog/sd_data_master.v
sd_card_controller/trunk/rtl/verilog/sd_crc_16.v
sd_card_controller/trunk/rtl/verilog/bistable_domain_cross.v
sd_card_controller/trunk/rtl/verilog/edge_detect.v
sd_card_controller/trunk/rtl/verilog/sd_cmd_serial_host.v
sd_card_controller/trunk/rtl/verilog/generic_fifo_dc_gray.v
sd_card_controller/trunk/rtl/verilog/sdc_controller.v
sd_card_controller/trunk/rtl/verilog/sd_fifo_filler.v
sd_card_controller/trunk/rtl/verilog/monostable_domain_cross.v
sd_card_controller/trunk/rtl/verilog/sd_defines.h
sd_card_controller/trunk/rtl/verilog/sd_data_xfer_trig.v
sd_card_controller/trunk/rtl/verilog/generic_dpram.v
sd_card_controller/trunk/rtl/verilog/sd_clock_divider.v
sd_card_controller/trunk/sw/
sd_card_controller/trunk/sw/example/
sd_card_controller/trunk/sw/example/.cproject
sd_card_controller/trunk/sw/example/.project
sd_card_controller/trunk/sw/example/.gitignore
sd_card_controller/trunk/sw/example/src/
sd_card_controller/trunk/sw/example/src/mmc.h
sd_card_controller/trunk/sw/example/src/ocsdc.c
sd_card_controller/trunk/sw/example/src/mmc.c
sd_card_controller/trunk/sw/example/src/sdc_example.c
sd_card_controller/tags/
sd_card_controller/branches/
sd_card_controller/trunk/
sd_card_controller/trunk/doc/
sd_card_controller/trunk/doc/bin/
sd_card_controller/trunk/doc/bin/ip_core.png
sd_card_controller/trunk/doc/bin/events.png
sd_card_controller/trunk/doc/bin/ip_core_if.png
sd_card_controller/trunk/doc/Wishbone SD Card Controller IP Specification.pdf
sd_card_controller/trunk/doc/references/
sd_card_controller/trunk/doc/references/part1_410.pdf
sd_card_controller/trunk/doc/src/
sd_card_controller/trunk/doc/src/events.odg
sd_card_controller/trunk/doc/src/usage.tex
sd_card_controller/trunk/doc/src/sw_if.tex
sd_card_controller/trunk/doc/src/introduction.tex
sd_card_controller/trunk/doc/src/specification.tex
sd_card_controller/trunk/doc/src/.gitignore
sd_card_controller/trunk/doc/src/ip_core_if.odg
sd_card_controller/trunk/doc/src/hdl_if.tex
sd_card_controller/trunk/doc/src/Makefile
sd_card_controller/trunk/doc/src/ip_core.odg
sd_card_controller/trunk/sim/
sd_card_controller/trunk/sim/rtl_sim/
sd_card_controller/trunk/sim/rtl_sim/run/
sd_card_controller/trunk/sim/rtl_sim/run/Makefile
sd_card_controller/trunk/sim/rtl_sim/bin/
sd_card_controller/trunk/sim/rtl_sim/bin/gui_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/ramdisk2.hex
sd_card_controller/trunk/sim/rtl_sim/bin/vcd_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/cli_startup.do
sd_card_controller/trunk/sim/rtl_sim/bin/wb_memory.txt
sd_card_controller/trunk/sim/rtl_sim/bin/FLASH.txt
sd_card_controller/trunk/sim/rtl_sim/bin/Makefile
sd_card_controller/trunk/README.md
sd_card_controller/trunk/bench/
sd_card_controller/trunk/bench/verilog/
sd_card_controller/trunk/bench/verilog/sd_cmd_serial_host_tb.sv
sd_card_controller/trunk/bench/verilog/sd_data_xfer_trig_tb.sv
sd_card_controller/trunk/bench/verilog/sd_controller_top_tb.sv
sd_card_controller/trunk/bench/verilog/edge_detect_tb.sv
sd_card_controller/trunk/bench/verilog/wb_slave_behavioral.v
sd_card_controller/trunk/bench/verilog/wb_bus_mon.v
sd_card_controller/trunk/bench/verilog/monostable_domain_cross_tb.sv
sd_card_controller/trunk/bench/verilog/wb_master32.v
sd_card_controller/trunk/bench/verilog/sd_data_master_tb.sv
sd_card_controller/trunk/bench/verilog/wb_master_behavioral.v
sd_card_controller/trunk/bench/verilog/sd_data_serial_host_tb.sv
sd_card_controller/trunk/bench/verilog/wb_model_defines.h
sd_card_controller/trunk/bench/verilog/bistable_domain_cross_tb.sv
sd_card_controller/trunk/bench/verilog/sd_cmd_master_tb.sv
sd_card_controller/trunk/bench/verilog/sd_fifo_filler_tb.sv
sd_card_controller/trunk/bench/verilog/sdModel.v
sd_card_controller/trunk/bench/verilog/sd_controller_wb_tb.sv
sd_card_controller/trunk/syn/
sd_card_controller/trunk/syn/quartus/
sd_card_controller/trunk/syn/quartus/run/
sd_card_controller/trunk/syn/quartus/run/Makefile
sd_card_controller/trunk/syn/quartus/bin/
sd_card_controller/trunk/syn/quartus/bin/pin_assignments.tcl
sd_card_controller/trunk/syn/quartus/bin/constraints.sdc
sd_card_controller/trunk/syn/quartus/bin/Makefile
sd_card_controller/trunk/syn/quartus/src/
sd_card_controller/trunk/syn/quartus/src/sdc_controller_top.v
sd_card_controller/trunk/rtl/
sd_card_controller/trunk/rtl/verilog/
sd_card_controller/trunk/rtl/verilog/sd_controller_wb.v
sd_card_controller/trunk/rtl/verilog/sd_data_serial_host.v
sd_card_controller/trunk/rtl/verilog/sd_crc_7.v
sd_card_controller/trunk/rtl/verilog/sd_cmd_master.v
sd_card_controller/trunk/rtl/verilog/sd_data_master.v
sd_card_controller/trunk/rtl/verilog/sd_crc_16.v
sd_card_controller/trunk/rtl/verilog/bistable_domain_cross.v
sd_card_controller/trunk/rtl/verilog/edge_detect.v
sd_card_controller/trunk/rtl/verilog/sd_cmd_serial_host.v
sd_card_controller/trunk/rtl/verilog/generic_fifo_dc_gray.v
sd_card_controller/trunk/rtl/verilog/sdc_controller.v
sd_card_controller/trunk/rtl/verilog/sd_fifo_filler.v
sd_card_controller/trunk/rtl/verilog/monostable_domain_cross.v
sd_card_controller/trunk/rtl/verilog/sd_defines.h
sd_card_controller/trunk/rtl/verilog/sd_data_xfer_trig.v
sd_card_controller/trunk/rtl/verilog/generic_dpram.v
sd_card_controller/trunk/rtl/verilog/sd_clock_divider.v
sd_card_controller/trunk/sw/
sd_card_controller/trunk/sw/example/
sd_card_controller/trunk/sw/example/.cproject
sd_card_controller/trunk/sw/example/.project
sd_card_controller/trunk/sw/example/.gitignore
sd_card_controller/trunk/sw/example/src/
sd_card_controller/trunk/sw/example/src/mmc.h
sd_card_controller/trunk/sw/example/src/ocsdc.c
sd_card_controller/trunk/sw/example/src/mmc.c
sd_card_controller/trunk/sw/example/src/sdc_example.c
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