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文件名称:88RISC-CPU

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2013-12-18
  • 文件大小：
    4.2mb
  • 已下载：
    0次
  • 提 供 者：
    倪***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

cpu设计能在quartus上运行 用verilog语言-a　cpu program use verilog on quartus
(系统自动生成,下载前可以参看下载内容)

下载文件列表

verilog-CPU/
verilog-CPU/CPU/
verilog-CPU/CPU/accum.v
verilog-CPU/CPU/accum.v.bak
verilog-CPU/CPU/adr.v
verilog-CPU/CPU/alu.v
verilog-CPU/CPU/alu.v.bak
verilog-CPU/CPU/clk_gen.v
verilog-CPU/CPU/clk_gen.v.bak
verilog-CPU/CPU/counter.v
verilog-CPU/CPU/CPU.asm.rpt
verilog-CPU/CPU/CPU.done
verilog-CPU/CPU/CPU.fit.rpt
verilog-CPU/CPU/CPU.fit.smsg
verilog-CPU/CPU/CPU.fit.summary
verilog-CPU/CPU/CPU.flow.rpt
verilog-CPU/CPU/CPU.map.rpt
verilog-CPU/CPU/CPU.map.summary
verilog-CPU/CPU/CPU.pin
verilog-CPU/CPU/CPU.qpf
verilog-CPU/CPU/CPU.qsf
verilog-CPU/CPU/CPU.sof
verilog-CPU/CPU/CPU.sta.rpt
verilog-CPU/CPU/CPU.sta.summary
verilog-CPU/CPU/datactl.v
verilog-CPU/CPU/datactl.v.bak
verilog-CPU/CPU/db/
verilog-CPU/CPU/db/CPU.(0).cnf.cdb
verilog-CPU/CPU/db/CPU.(0).cnf.hdb
verilog-CPU/CPU/db/CPU.amm.cdb
verilog-CPU/CPU/db/CPU.asm.qmsg
verilog-CPU/CPU/db/CPU.asm.rdb
verilog-CPU/CPU/db/CPU.asm_labs.ddb
verilog-CPU/CPU/db/CPU.cbx.xml
verilog-CPU/CPU/db/CPU.cmp.bpm
verilog-CPU/CPU/db/CPU.cmp.cdb
verilog-CPU/CPU/db/CPU.cmp.hdb
verilog-CPU/CPU/db/CPU.cmp.kpt
verilog-CPU/CPU/db/CPU.cmp.logdb
verilog-CPU/CPU/db/CPU.cmp.rdb
verilog-CPU/CPU/db/CPU.cmp_merge.kpt
verilog-CPU/CPU/db/CPU.db_info
verilog-CPU/CPU/db/CPU.fit.qmsg
verilog-CPU/CPU/db/CPU.hier_info
verilog-CPU/CPU/db/CPU.hif
verilog-CPU/CPU/db/CPU.idb.cdb
verilog-CPU/CPU/db/CPU.lpc.html
verilog-CPU/CPU/db/CPU.lpc.rdb
verilog-CPU/CPU/db/CPU.lpc.txt
verilog-CPU/CPU/db/CPU.map.bpm
verilog-CPU/CPU/db/CPU.map.cdb
verilog-CPU/CPU/db/CPU.map.hdb
verilog-CPU/CPU/db/CPU.map.kpt
verilog-CPU/CPU/db/CPU.map.logdb
verilog-CPU/CPU/db/CPU.map.qmsg
verilog-CPU/CPU/db/CPU.map_bb.cdb
verilog-CPU/CPU/db/CPU.map_bb.hdb
verilog-CPU/CPU/db/CPU.map_bb.logdb
verilog-CPU/CPU/db/CPU.pre_map.cdb
verilog-CPU/CPU/db/CPU.pre_map.hdb
verilog-CPU/CPU/db/CPU.rtlv.hdb
verilog-CPU/CPU/db/CPU.rtlv_sg.cdb
verilog-CPU/CPU/db/CPU.rtlv_sg_swap.cdb
verilog-CPU/CPU/db/CPU.sgdiff.cdb
verilog-CPU/CPU/db/CPU.sgdiff.hdb
verilog-CPU/CPU/db/CPU.sld_design_entry.sci
verilog-CPU/CPU/db/CPU.sld_design_entry_dsc.sci
verilog-CPU/CPU/db/CPU.smart_action.txt
verilog-CPU/CPU/db/CPU.smp_dump.txt
verilog-CPU/CPU/db/CPU.sta.qmsg
verilog-CPU/CPU/db/CPU.sta.rdb
verilog-CPU/CPU/db/CPU.sta_cmp.7_slow_1200mv_85c.tdb
verilog-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
verilog-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ii_1200mv_0c_slow.hsd
verilog-CPU/CPU/db/CPU.stingray_io_sim_cache.45um_ii_1200mv_85c_slow.hsd
verilog-CPU/CPU/db/CPU.syn_hier_info
verilog-CPU/CPU/db/CPU.tiscmp.fastest_slow_1200mv_0c.ddb
verilog-CPU/CPU/db/CPU.tiscmp.fastest_slow_1200mv_85c.ddb
verilog-CPU/CPU/db/CPU.tiscmp.fast_1200mv_0c.ddb
verilog-CPU/CPU/db/CPU.tiscmp.slow_1200mv_0c.ddb
verilog-CPU/CPU/db/CPU.tiscmp.slow_1200mv_85c.ddb
verilog-CPU/CPU/db/CPU.tis_db_list.ddb
verilog-CPU/CPU/db/logic_util_heursitic.dat
verilog-CPU/CPU/db/prev_cmp_CPU.qmsg
verilog-CPU/CPU/incremental_db/
verilog-CPU/CPU/incremental_db/compiled_partitions/
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.db_info
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.cdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcfdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.cdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.cdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hb_info
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.hdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hbdb.sig
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hdb
verilog-CPU/CPU/incremental_db/compiled_partitions/CPU.root_partition.map.kpt
verilog-CPU/CPU/incremental_db/README
verilog-CPU/CPU/machine.v
verilog-CPU/CPU/machine.v.bak
verilog-CPU/CPU/machinectl.v.bak
verilog-CPU/CPU/register.v
verilog-CPU/CPU/register.v.bak
verilog-CPU/CPU/rom_ram.v
verilog-CPU/CPU/rom_ram.v.bak
verilog-CPU/CPU_sim/
verilog-CPU/CPU_sim/accum.v
verilog-CPU/CPU_sim/addr_decode.v
verilog-CPU/CPU_sim/adr.v
verilog-CPU/CPU_sim/alu.v
verilog-CPU/CPU_sim/clk_gen.v
verilog-CPU/CPU_sim/counter.v
verilog-CPU/CPU_sim/CPU.cr.mti
verilog-CPU/CPU_sim/CPU.mpf
verilog-CPU/CPU_sim/cpu.v
verilog-CPU/CPU_sim/cpu.v.bak
verilog-CPU/CPU_sim/cputop.v
verilog-CPU/CPU_sim/cputop.v.bak
verilog-CPU/CPU_sim/datactl.v
verilog-CPU/CPU_sim/machine.v
verilog-CPU/CPU_sim/machine.v.bak
verilog-CPU/CPU_sim/machinectl.v
verilog-CPU/CPU_sim/my_state_test.v
verilog-CPU/CPU_sim/my_state_test.v.bak
verilog-CPU/CPU_sim/register.v
verilog-CPU/CPU_sim/rom_ram.v
verilog-CPU/CPU_sim/tcl_stacktrace.txt
verilog-CPU/CPU_sim/test1.dat
verilog-CPU/CPU_sim/test1.pro
verilog-CPU/CPU_s

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