文件名称:RISC_Core.ZIP
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这是一篇关于8位RISC CPU设计的文章,其中包含了用Verilog语言编写的CPU内核程序
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog/doc/
verilog/doc/risc8.pdf
verilog/doc/risc8.ps
verilog/src/
verilog/src/risc8.v
verilog/src/risc8_alu.v
verilog/src/rbcla_adder.v
verilog/src/risc8_control.v
verilog/src/risc8_regb_biu.v
verilog/src/risc8_constants.v
verilog/src/risc8_parameters.v
verilog/sim/
verilog/sim/compile
verilog/sim/regression
verilog/sim/test.v
verilog/sim/run_interac
verilog/sim/test.mem
verilog/sim/risc8.cfg
verilog/sim/reg.mem
verilog/sim/run_batch
verilog/sim/DW01_add.v
verilog/sim/asm/
verilog/sim/asm/and.mem
verilog/sim/asm/and.asm
verilog/sim/asm/arith.mem
verilog/sim/asm/or.asm
verilog/sim/asm/arith.asm
verilog/sim/asm/jmp.mem
verilog/sim/asm/loadstore.asm
verilog/sim/asm/logic.mem
verilog/sim/asm/or.mem
verilog/sim/asm/moves.asm
verilog/sim/asm/divide.mem
verilog/sim/asm/moves.mem
verilog/sim/asm/waitstates.asm
verilog/sim/asm/assemble_all
verilog/sim/asm/interrupt.asm
verilog/sim/asm/interrupt.mem
verilog/sim/asm/logic.asm
verilog/sim/asm/jmp.asm
verilog/sim/asm/flags.asm
verilog/sim/asm/divide.asm
verilog/sim/asm/loadstore.mem
verilog/sim/asm/flags.mem
verilog/sim/asm/multiply.asm
verilog/sim/asm/multiply.mem
verilog/sim/asm/waitstates.mem
verilog/sim/asm/staldapshpop.asm
verilog/sim/asm/staldapshpop.mem
verilog/bin/
verilog/bin/risc8_asm.pl
verilog/bin/example.asm
verilog/bin/example.mem
verilog/bin/example.hex
verilog/syn/
verilog/syn/risc8_dc_compile.scr
verilog/
example_asm.txt
risc8.pdf
risc8_asm_pl.txt
risc8_tar.gz
verilog/doc/risc8.pdf
verilog/doc/risc8.ps
verilog/src/
verilog/src/risc8.v
verilog/src/risc8_alu.v
verilog/src/rbcla_adder.v
verilog/src/risc8_control.v
verilog/src/risc8_regb_biu.v
verilog/src/risc8_constants.v
verilog/src/risc8_parameters.v
verilog/sim/
verilog/sim/compile
verilog/sim/regression
verilog/sim/test.v
verilog/sim/run_interac
verilog/sim/test.mem
verilog/sim/risc8.cfg
verilog/sim/reg.mem
verilog/sim/run_batch
verilog/sim/DW01_add.v
verilog/sim/asm/
verilog/sim/asm/and.mem
verilog/sim/asm/and.asm
verilog/sim/asm/arith.mem
verilog/sim/asm/or.asm
verilog/sim/asm/arith.asm
verilog/sim/asm/jmp.mem
verilog/sim/asm/loadstore.asm
verilog/sim/asm/logic.mem
verilog/sim/asm/or.mem
verilog/sim/asm/moves.asm
verilog/sim/asm/divide.mem
verilog/sim/asm/moves.mem
verilog/sim/asm/waitstates.asm
verilog/sim/asm/assemble_all
verilog/sim/asm/interrupt.asm
verilog/sim/asm/interrupt.mem
verilog/sim/asm/logic.asm
verilog/sim/asm/jmp.asm
verilog/sim/asm/flags.asm
verilog/sim/asm/divide.asm
verilog/sim/asm/loadstore.mem
verilog/sim/asm/flags.mem
verilog/sim/asm/multiply.asm
verilog/sim/asm/multiply.mem
verilog/sim/asm/waitstates.mem
verilog/sim/asm/staldapshpop.asm
verilog/sim/asm/staldapshpop.mem
verilog/bin/
verilog/bin/risc8_asm.pl
verilog/bin/example.asm
verilog/bin/example.mem
verilog/bin/example.hex
verilog/syn/
verilog/syn/risc8_dc_compile.scr
verilog/
example_asm.txt
risc8.pdf
risc8_asm_pl.txt
risc8_tar.gz
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