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文件名称:t4_fifo

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-03-05
  • 文件大小：
    228.76kb
  • 已下载：
    0次
  • 提 供 者：
    宋****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want to be useful.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

t4_fifo/db/altsyncram_8sj1.tdf
t4_fifo/db/altsyncram_amc1.tdf
t4_fifo/db/altsyncram_oog1.tdf
t4_fifo/db/a_dpfifo_gj31.tdf
t4_fifo/db/a_fefifo_08f.tdf
t4_fifo/db/cntr_hjb.tdf
t4_fifo/db/cntr_tj7.tdf
t4_fifo/db/dpram_0u01.tdf
t4_fifo/db/logic_util_heursitic.dat
t4_fifo/db/prev_cmp_t4_fifo.qmsg
t4_fifo/db/scfifo_9d31.tdf
t4_fifo/db/t4_fifo.(0).cnf.cdb
t4_fifo/db/t4_fifo.(0).cnf.hdb
t4_fifo/db/t4_fifo.(1).cnf.cdb
t4_fifo/db/t4_fifo.(1).cnf.hdb
t4_fifo/db/t4_fifo.(2).cnf.cdb
t4_fifo/db/t4_fifo.(2).cnf.hdb
t4_fifo/db/t4_fifo.cbx.xml
t4_fifo/db/t4_fifo.cmp.rdb
t4_fifo/db/t4_fifo.cmp_merge.kpt
t4_fifo/db/t4_fifo.db_info
t4_fifo/db/t4_fifo.hier_info
t4_fifo/db/t4_fifo.hif
t4_fifo/db/t4_fifo.lpc.html
t4_fifo/db/t4_fifo.lpc.rdb
t4_fifo/db/t4_fifo.lpc.txt
t4_fifo/db/t4_fifo.map.bpm
t4_fifo/db/t4_fifo.map.cdb
t4_fifo/db/t4_fifo.map.hdb
t4_fifo/db/t4_fifo.map.kpt
t4_fifo/db/t4_fifo.map.logdb
t4_fifo/db/t4_fifo.map.qmsg
t4_fifo/db/t4_fifo.map.rdb
t4_fifo/db/t4_fifo.map_bb.cdb
t4_fifo/db/t4_fifo.map_bb.hdb
t4_fifo/db/t4_fifo.map_bb.logdb
t4_fifo/db/t4_fifo.pre_map.cdb
t4_fifo/db/t4_fifo.pre_map.hdb
t4_fifo/db/t4_fifo.root_partition.map.reg_db.cdb
t4_fifo/db/t4_fifo.rtlv.hdb
t4_fifo/db/t4_fifo.rtlv_sg.cdb
t4_fifo/db/t4_fifo.rtlv_sg_swap.cdb
t4_fifo/db/t4_fifo.sgdiff.cdb
t4_fifo/db/t4_fifo.sgdiff.hdb
t4_fifo/db/t4_fifo.sld_design_entry.sci
t4_fifo/db/t4_fifo.sld_design_entry_dsc.sci
t4_fifo/db/t4_fifo.smart_action.txt
t4_fifo/db/t4_fifo.syn_hier_info
t4_fifo/db/t4_fifo.tis_db_list.ddb
t4_fifo/fifo_verilog.bsf
t4_fifo/fifo_verilog.v
t4_fifo/fifo_verilog.v.bak
t4_fifo/fifo_verilog_tb.v
t4_fifo/fifo_verilog_tb.v.bak
t4_fifo/greybox_tmp/cbx_args.txt
t4_fifo/incremental_db/compiled_partitions/t4_fifo.db_info
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.cdb
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.dpi
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.hbdb.cdb
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.hbdb.hb_info
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.hbdb.hdb
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.hbdb.sig
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.hdb
t4_fifo/incremental_db/compiled_partitions/t4_fifo.root_partition.map.kpt
t4_fifo/incremental_db/README
t4_fifo/my_fifo.bsf
t4_fifo/my_fifo.cmp
t4_fifo/my_fifo.qip
t4_fifo/my_fifo.vhd
t4_fifo/my_fifo_tb.vhd
t4_fifo/my_fifo_tb.vhd.bak
t4_fifo/simulation/modelsim/modelsim.ini
t4_fifo/simulation/modelsim/msim_transcript
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog/verilog.prw
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog/verilog.psm
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog/_primary.dat
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog/_primary.dbs
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog/_primary.vhd
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb/verilog.prw
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb/verilog.psm
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb/_primary.dat
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb/_primary.dbs
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb/_primary.vhd
t4_fifo/simulation/modelsim/rtl_work/_info
t4_fifo/simulation/modelsim/rtl_work/_vmake
t4_fifo/simulation/modelsim/t4_fifo_run_msim_rtl_verilog.do
t4_fifo/simulation/modelsim/t4_fifo_run_msim_rtl_verilog.do.bak
t4_fifo/simulation/modelsim/t4_fifo_run_msim_rtl_vhdl.do
t4_fifo/simulation/modelsim/t4_fifo_run_msim_rtl_vhdl.do.bak
t4_fifo/simulation/modelsim/vsim.wlf
t4_fifo/t4_fifo.bdf
t4_fifo/t4_fifo.done
t4_fifo/t4_fifo.flow.rpt
t4_fifo/t4_fifo.map.rpt
t4_fifo/t4_fifo.map.summary
t4_fifo/t4_fifo.qpf
t4_fifo/t4_fifo.qsf
t4_fifo/t4_fifo.qws
t4_fifo/t4_fifo_assignment_defaults.qdf
t4_fifo/t4_fifo_nativelink_simulation.rpt
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog
t4_fifo/simulation/modelsim/rtl_work/fifo_verilog_tb
t4_fifo/simulation/modelsim/rtl_work/_temp
t4_fifo/simulation/modelsim/rtl_work
t4_fifo/incremental_db/compiled_partitions
t4_fifo/simulation/modelsim
t4_fifo/db
t4_fifo/greybox_tmp
t4_fifo/incremental_db
t4_fifo/simulation
t4_fifo

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