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文件名称:AD7865

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2014-05-06
  • 文件大小：
    448.96kb
  • 已下载：
    0次
  • 提 供 者：
    叶***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog HDL语言编写的16位AD采样程序，包含源码和测试文件，已通过测试-verilog HDL language 16 AD sampling procedures, including source code and test files, has been tested
(系统自动生成,下载前可以参看下载内容)

下载文件列表

AD7865/AD7865.asm.rpt
AD7865/AD7865.done
AD7865/AD7865.eda.rpt
AD7865/AD7865.fit.rpt
AD7865/AD7865.fit.smsg
AD7865/AD7865.fit.summary
AD7865/AD7865.flow.rpt
AD7865/AD7865.map.rpt
AD7865/AD7865.map.summary
AD7865/AD7865.out.sdc
AD7865/AD7865.pin
AD7865/AD7865.pof
AD7865/AD7865.qpf
AD7865/AD7865.qsf
AD7865/AD7865.sdc
AD7865/AD7865.sof
AD7865/AD7865.sta.rpt
AD7865/AD7865.sta.summary
AD7865/AD7865.tis_db_list.ddb
AD7865/AD7865.v
AD7865/AD7865.v.bak
AD7865/AD7865_nativelink_simulation.rpt
AD7865/db/AD7865.(0).cnf.cdb
AD7865/db/AD7865.(0).cnf.hdb
AD7865/db/AD7865.ace_cmp.bpm
AD7865/db/AD7865.ace_cmp.cdb
AD7865/db/AD7865.ace_cmp.hdb
AD7865/db/AD7865.amm.cdb
AD7865/db/AD7865.asm.qmsg
AD7865/db/AD7865.asm.rdb
AD7865/db/AD7865.asm_labs.ddb
AD7865/db/AD7865.cbx.xml
AD7865/db/AD7865.cmp.bpm
AD7865/db/AD7865.cmp.cdb
AD7865/db/AD7865.cmp.hdb
AD7865/db/AD7865.cmp.kpt
AD7865/db/AD7865.cmp.logdb
AD7865/db/AD7865.cmp.rdb
AD7865/db/AD7865.cmp0.ddb
AD7865/db/AD7865.cmp1.ddb
AD7865/db/AD7865.cmp2.ddb
AD7865/db/AD7865.cmp_merge.kpt
AD7865/db/AD7865.db_info
AD7865/db/AD7865.eco.cdb
AD7865/db/AD7865.eda.qmsg
AD7865/db/AD7865.fit.qmsg
AD7865/db/AD7865.hier_info
AD7865/db/AD7865.hif
AD7865/db/AD7865.idb.cdb
AD7865/db/AD7865.lpc.html
AD7865/db/AD7865.lpc.rdb
AD7865/db/AD7865.lpc.txt
AD7865/db/AD7865.map.bpm
AD7865/db/AD7865.map.cdb
AD7865/db/AD7865.map.hdb
AD7865/db/AD7865.map.kpt
AD7865/db/AD7865.map.logdb
AD7865/db/AD7865.map.qmsg
AD7865/db/AD7865.map_bb.cdb
AD7865/db/AD7865.map_bb.hdb
AD7865/db/AD7865.map_bb.logdb
AD7865/db/AD7865.pre_map.cdb
AD7865/db/AD7865.pre_map.hdb
AD7865/db/AD7865.rpp.qmsg
AD7865/db/AD7865.rtlv.hdb
AD7865/db/AD7865.rtlv_sg.cdb
AD7865/db/AD7865.rtlv_sg_swap.cdb
AD7865/db/AD7865.sgate.rvd
AD7865/db/AD7865.sgate_sm.rvd
AD7865/db/AD7865.sgdiff.cdb
AD7865/db/AD7865.sgdiff.hdb
AD7865/db/AD7865.sld_design_entry.sci
AD7865/db/AD7865.sld_design_entry_dsc.sci
AD7865/db/AD7865.smart_action.txt
AD7865/db/AD7865.sta.qmsg
AD7865/db/AD7865.sta.rdb
AD7865/db/AD7865.sta_cmp.8_slow.tdb
AD7865/db/AD7865.syn_hier_info
AD7865/db/AD7865.tan.qmsg
AD7865/db/AD7865.taw.rdb
AD7865/db/AD7865.tis_db_list.ddb
AD7865/db/logic_util_heursitic.dat
AD7865/db/prev_cmp_AD7865.qmsg
AD7865/incremental_db/compiled_partitions/AD7865.db_info
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.cdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.dfp
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.hdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.kpt
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.logdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.cmp.rcfdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.cdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.dpi
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.hbdb.cdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.hbdb.hb_info
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.hbdb.hdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.hbdb.sig
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.hdb
AD7865/incremental_db/compiled_partitions/AD7865.root_partition.map.kpt
AD7865/incremental_db/README
AD7865/simulation/modelsim/AD7865.sft
AD7865/simulation/modelsim/AD7865.vo
AD7865/simulation/modelsim/AD7865.vt
AD7865/simulation/modelsim/AD7865.vt.bak
AD7865/simulation/modelsim/AD7865_fast.vo
AD7865/simulation/modelsim/AD7865_modelsim.xrf
AD7865/simulation/modelsim/AD7865_run_msim_gate_verilog.do
AD7865/simulation/modelsim/AD7865_run_msim_gate_verilog.do.bak
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak1
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak10
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak11
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak2
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak3
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak4
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak5
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak6
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak7
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak8
AD7865/simulation/modelsim/AD7865_run_msim_rtl_verilog.do.bak9
AD7865/simulation/modelsim/AD7865_v.sdo
AD7865/simulation/modelsim/AD7865_v.sdo_typ.csd
AD7865/simulation/modelsim/AD7865_v_fast.sdo
AD7865/simulation/modelsim/AD7865_v_fast.sdo_typ.csd
AD7865/simulation/modelsim/gate_work/@a@d7865/verilog.prw
AD7865/simulation/modelsim/gate_work/@a@d7865/verilog.psm
AD7865/simulation/modelsim/gate_work/@a@d7865/_primary.dat
AD7865/simulation/modelsim/gate_work/@a@d7865/_primary.dbs
AD7865/simulation/modelsim/gate_work/@a@d7865/_primary.vhd
AD7865/simulation/modelsim/gate_work/@a@d7865_vlg_tst/verilog.prw
AD7865/simulation/modelsim/gate_work/@a@d7865_vlg_tst/verilog.psm
AD7865/simulation/models

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