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work/work/reg5/_primary.vhd
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work/work/reg3/_primary.vhd
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work/work/reg2/_primary.vhd
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work/work/reg1/_primary.vhd
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work/work/multiply/_primary.vhd
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work/work/@indi@addr/_primary.vhd
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work/work/ext_addr_sel/_primary.vhd
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work/work/divide/_primary.vhd
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work/work/alu_src3_sel/_primary.vhd
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work/work/all/_primary.vhd
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work/work/tb_all/_primary.vhd
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work/decode2_4.v
work/decode2_4.v.bak
work/aaa.mpf
work/aaa.cr.mti
work/ALU.v
work/8051.mpf
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work/Acc.v
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work/alu_src1_sel.v
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work/Comp.v
work/cy_select.v
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work/Defines.v
work/Divide.v
work/Dptr.v
work/ext_addr_sel.v
work/immediate_sel.v
work/IndiAddr.v
work/Make
work/Multiply.v
work/op_select.v
work/Pc.v
work/Port_out.v
work/Psw.v
work/Ram.v
work/ram_rd_sel.v
work/Ram_sel.v
work/ram_wr_sel.v
work/Reg1.v
work/Reg2.v
work/Reg3.v
work/Reg4.v
work/Reg5.v
work/Reg8.v
work/Reg8r.v
work/Rom.v
work/rom_addr_sel.v
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work/transcript
work/vish_stacktrace.vstf
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work/work/tb_all
work/work
work