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文件名称:lab5

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  • 上传时间:
    2014-05-07
  • 文件大小:
    15.37mb
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介绍说明--下载内容来自于网络,使用问题请自行百度

用Xilinx内核生成器系统生成DCM内核

和存储器内核(ROM、RAM)等-DCM core and memory cores generated by Xilinx CORE Generator System (ROM, RAM), etc.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

lab5/data/ascii.coe
lab5/data/flower1_128x128.coe
lab5/data/flower2_128x128.coe
lab5/IPCore/IPCore.ipf
lab5/IPCore/IPCore.ise
lab5/IPCore/IPCore.ise_ISE_Backup
lab5/IPCore/IPCore.ntrc_log
lab5/IPCore/IPCore.restore
lab5/IPCore/ipcore_top.bgn
lab5/IPCore/ipcore_top.bit
lab5/IPCore/IPCore_top.bld
lab5/IPCore/IPCore_top.cmd_log
lab5/IPCore/ipcore_top.drc
lab5/IPCore/IPCore_top.lso
lab5/IPCore/IPCore_top.ncd
lab5/IPCore/IPCore_top.ngc
lab5/IPCore/IPCore_top.ngd
lab5/IPCore/IPCore_top.ngr
lab5/IPCore/IPCore_top.pad
lab5/IPCore/IPCore_top.par
lab5/IPCore/IPCore_top.pcf
lab5/IPCore/IPCore_top.prj
lab5/IPCore/IPCore_top.stx
lab5/IPCore/IPCore_top.syr
lab5/IPCore/ipcore_top.twr
lab5/IPCore/ipcore_top.twx
lab5/IPCore/IPCore_top.unroutes
lab5/IPCore/IPCore_top.ut
lab5/IPCore/IPCore_top.xpi
lab5/IPCore/IPCore_top.xst
lab5/IPCore/IPCore_top_guide.ncd
lab5/IPCore/IPCore_top_map.map
lab5/IPCore/IPCore_top_map.mrp
lab5/IPCore/IPCore_top_map.ncd
lab5/IPCore/IPCore_top_map.ngm
lab5/IPCore/IPCore_top_pad.csv
lab5/IPCore/IPCore_top_pad.txt
lab5/IPCore/IPCore_top_prev_built.ngd
lab5/IPCore/IPCore_top_summary.html
lab5/IPCore/IPCore_top_summary.xml
lab5/IPCore/IPCore_top_usage.xml
lab5/IPCore/PictureROM.asy
lab5/IPCore/PictureROM.mif
lab5/IPCore/PictureROM.ngc
lab5/IPCore/PictureROM.sym
lab5/IPCore/PictureROM.v
lab5/IPCore/PictureROM.veo
lab5/IPCore/PictureROM.vhd
lab5/IPCore/PictureROM.vho
lab5/IPCore/PictureROM.xco
lab5/IPCore/PictureROM_flist.txt
lab5/IPCore/PictureROM_readme.txt
lab5/IPCore/PictureROM_xmdf.tcl
lab5/IPCore/templates/coregen.xml
lab5/IPCore/tmp/_cg/PictureROM.mif
lab5/IPCore/transcript
lab5/IPCore/VgaDCM.tfi
lab5/IPCore/VgaDCM.v
lab5/IPCore/VgaDCM.xaw
lab5/IPCore/VgaDCM_arwz.ucf
lab5/IPCore/xaw2verilog.log
lab5/IPCore/xst/dump.xst/IPCore_top.prj/ntrc.scr
lab5/IPCore/xst/work/hdllib.ref
lab5/IPCore/xst/work/vlg0A/_picture_r_o_m.bin
lab5/IPCore/xst/work/vlg45/svga__ctrl.bin
lab5/IPCore/xst/work/vlg4C/_i_p_core__top.bin
lab5/IPCore/xst/work/vlg62/_vga_d_c_m.bin
lab5/IPCore/_impact.cmd
lab5/IPCore/_impact.log
lab5/IPCore/_ngo/netlist.lst
lab5/IPCore/_xmsgs/bitgen.xmsgs
lab5/IPCore/_xmsgs/map.xmsgs
lab5/IPCore/_xmsgs/ngdbuild.xmsgs
lab5/IPCore/_xmsgs/par.xmsgs
lab5/IPCore/_xmsgs/trce.xmsgs
lab5/IPCore/_xmsgs/xst.xmsgs
lab5/sim/IPCoreSim.cr.mti
lab5/sim/IPCoreSim.mpf
lab5/sim/PictureROM.mif
lab5/sim/rgb.rgb24
lab5/sim/vsim.wlf
lab5/sim/work/@i@p@core_svga_tb/verilog.asm
lab5/sim/work/@i@p@core_svga_tb/_primary.dat
lab5/sim/work/@i@p@core_svga_tb/_primary.vhd
lab5/sim/work/@i@p@core_top/verilog.asm
lab5/sim/work/@i@p@core_top/_primary.dat
lab5/sim/work/@i@p@core_top/_primary.vhd
lab5/sim/work/@picture@r@o@m/verilog.asm
lab5/sim/work/@picture@r@o@m/_primary.dat
lab5/sim/work/@picture@r@o@m/_primary.vhd
lab5/sim/work/@vga@d@c@m/verilog.asm
lab5/sim/work/@vga@d@c@m/_primary.dat
lab5/sim/work/@vga@d@c@m/_primary.vhd
lab5/sim/work/svga_ctrl/verilog.asm
lab5/sim/work/svga_ctrl/_primary.dat
lab5/sim/work/svga_ctrl/_primary.vhd
lab5/sim/work/_info
lab5/sim/work/_opt/C
lab5/sim/work/_opt/work_@i@p@core_svga_tb_fast.asm
lab5/sim/work/_opt/work_@i@p@core_svga_tb_fast.dt2
lab5/sim/work/_opt/work_@i@p@core_top_fast.asm
lab5/sim/work/_opt/work_@i@p@core_top_fast.dt2
lab5/sim/work/_opt/work_@picture@r@o@m_fast.asm
lab5/sim/work/_opt/work_@picture@r@o@m_fast.dt2
lab5/sim/work/_opt/work_@vga@d@c@m_fast.asm
lab5/sim/work/_opt/work_@vga@d@c@m_fast.dt2
lab5/sim/work/_opt/work_svga_ctrl_fast.asm
lab5/sim/work/_opt/work_svga_ctrl_fast.dt2
lab5/sim/work/_opt/_deps
lab5/src/IPCore.ucf
lab5/src/IPCore_svga_tb.v
lab5/src/IPcore_top.v
lab5/src/svga_ctrl.v
lab5/IPCore/xst/dump.xst/IPCore_top.prj/ngx/notopt
lab5/IPCore/xst/dump.xst/IPCore_top.prj/ngx/opt
lab5/IPCore/xst/dump.xst/IPCore_top.prj/ngx
lab5/IPCore/xst/dump.xst/IPCore_top.prj
lab5/IPCore/xst/work/vlg0A
lab5/IPCore/xst/work/vlg45
lab5/IPCore/xst/work/vlg4C
lab5/IPCore/xst/work/vlg62
lab5/IPCore/tmp/_cg
lab5/IPCore/xst/dump.xst
lab5/IPCore/xst/projnav.tmp
lab5/IPCore/xst/work
lab5/sim/work/@i@p@core_svga_tb
lab5/sim/work/@i@p@core_top
lab5/sim/work/@picture@r@o@m
lab5/sim/work/@vga@d@c@m
lab5/sim/work/svga_ctrl
lab5/sim/work/_opt
lab5/IPCore/templates
lab5/IPCore/tmp
lab5/IPCore/xst
lab5/IPCore/_ngo
lab5/IPCore/_xmsgs
lab5/sim/work
lab5/data
lab5/IPCore
lab5/sim
lab5/src
lab5

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