文件名称:FPGA-logic-designer-test
-
所属分类:
- 标签属性:
- 上传时间:2014-05-18
-
文件大小:2.96mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
该文件包含了FPGA逻辑设计实验的相关代码,提供了ISE平台下可直接运行的代码-This file contains the FPGA logic design experiments related code, provides the code can be run directly under the ISE platform
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA逻辑设计实验/
FPGA逻辑设计实验/lab1/
FPGA逻辑设计实验/lab2/
FPGA逻辑设计实验/lab2/arwz_pace.dhp
FPGA逻辑设计实验/lab2/arwz_pace.ise
FPGA逻辑设计实验/lab2/arwz_pace.ise.old
FPGA逻辑设计实验/lab2/arwz_pace.ise_8.1i_backup
FPGA逻辑设计实验/lab2/arwz_pace.ise_ISE_Backup
FPGA逻辑设计实验/lab2/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab2/kcpsm3.vhd
FPGA逻辑设计实验/lab2/kcuart_rx.vhd
FPGA逻辑设计实验/lab2/kcuart_tx.vhd
FPGA逻辑设计实验/lab2/uart_clock.vhd
FPGA逻辑设计实验/lab2/uart_clock_summary.html
FPGA逻辑设计实验/lab2/uart_rx.vhd
FPGA逻辑设计实验/lab2/uart_tx.vhd
FPGA逻辑设计实验/lab2/UCLOCK.VHD
FPGA逻辑设计实验/lab2/_xmsgs/
FPGA逻辑设计实验/lab3/
FPGA逻辑设计实验/lab3/Assembler/
FPGA逻辑设计实验/lab3/Assembler/assemble.bat
FPGA逻辑设计实验/lab3/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab3/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab3/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab3/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab3/Assembler/program.psm
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab3/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab3/Assembler/ROM_form.v
FPGA逻辑设计实验/lab3/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab3/loopback.vhd
FPGA逻辑设计实验/lab3/testbench.vhd
FPGA逻辑设计实验/lab3/time_const/
FPGA逻辑设计实验/lab3/time_const/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab3/time_const/isim.hdlsourcefiles
FPGA逻辑设计实验/lab3/time_const/isim.log
FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/
FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/_1
FPGA逻辑设计实验/lab3/time_const/isimwavedata.xwv
FPGA逻辑设计实验/lab3/time_const/kcpsm3.vhd
FPGA逻辑设计实验/lab3/time_const/kcuart_rx.vhd
FPGA逻辑设计实验/lab3/time_const/kcuart_tx.vhd
FPGA逻辑设计实验/lab3/time_const/loopback.vhd
FPGA逻辑设计实验/lab3/time_const/loopback_summary.html
FPGA逻辑设计实验/lab3/time_const/my_dcm.xaw
FPGA逻辑设计实验/lab3/time_const/Project.dhp
FPGA逻辑设计实验/lab3/time_const/time_const.dhp
FPGA逻辑设计实验/lab3/time_const/time_const.ise
FPGA逻辑设计实验/lab3/time_const/time_const.ise.old
FPGA逻辑设计实验/lab3/time_const/time_const.ise_8.1i_backup
FPGA逻辑设计实验/lab3/time_const/time_const.ise_ISE_Backup
FPGA逻辑设计实验/lab3/time_const/uart_rx.vhd
FPGA逻辑设计实验/lab3/time_const/uart_tx.vhd
FPGA逻辑设计实验/lab3/time_const/_xmsgs/
FPGA逻辑设计实验/lab3/time_const/_xmsgs/fuse.xmsgs
FPGA逻辑设计实验/lab3/time_const/_xmsgs/vhpcomp.xmsgs
FPGA逻辑设计实验/lab4/
FPGA逻辑设计实验/lab4/Assembler/
FPGA逻辑设计实验/lab4/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab4/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab4/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab4/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab4/Assembler/program.psm
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab4/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab4/Assembler/ROM_form.v
FPGA逻辑设计实验/lab4/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab4/synth_lab/
FPGA逻辑设计实验/lab4/synth_lab/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcpsm3.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcuart_rx.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcuart_tx.vhd
FPGA逻辑设计实验/lab4/synth_lab/loopback.ucf
FPGA逻辑设计实验/lab4/synth_lab/loopback.ut
FPGA逻辑设计实验/lab4/synth_lab/loopback.vhd
FPGA逻辑设计实验/lab4/synth_lab/loopback_prev_built.ngd
FPGA逻辑设计实验/lab4/synth_lab/loopback_summary.html
FPGA逻辑设计实验/lab4/synth_lab/my_dcm.xaw
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise_ISE_Backup
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ntrc_log
FPGA逻辑设计实验/lab4/synth_lab/testbench.vhd
FPGA逻辑设计实验/lab4/synth_lab/uart_rx.vhd
FPGA逻辑设计实验/lab4/synth_lab/uart_tx.vhd
FPGA逻辑设计实验/lab4/synth_lab/_impact.cmd
FPGA逻辑设计实验/lab4/synth_lab/_impact.log
FPGA逻辑设计实验/lab4/synth_lab/_xmsgs/
FPGA逻辑设计实验/lab5/
FPGA逻辑设计实验/lab5/Assembler/
FPGA逻辑设计实验/lab5/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab5/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab5/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab5/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab5/Assembler/program.psm
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab5/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab5/Assembler/ROM_form.v
FPGA逻辑设计实验/lab5/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab5/coregen/
FPGA逻辑设计实验/lab5/coregen/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab5/coregen/coregen.ise
FPGA逻辑设计实验/lab5/coregen/coregen.ise_ISE_Backup
FPGA逻辑设计实验/lab5/coregen/coregen_ise9migration.zip
FPGA逻辑设计实验/lab5/coregen/kcpsm3.vhd
FPGA逻辑设计实验/lab5/coregen/kcuart_rx.vhd
FPGA逻辑设计实验/lab5/coregen/kcuart_tx.vhd
FPGA逻辑设计实验/
FPGA逻辑设计实验/lab1/
FPGA逻辑设计实验/lab2/
FPGA逻辑设计实验/lab2/arwz_pace.dhp
FPGA逻辑设计实验/lab2/arwz_pace.ise
FPGA逻辑设计实验/lab2/arwz_pace.ise.old
FPGA逻辑设计实验/lab2/arwz_pace.ise_8.1i_backup
FPGA逻辑设计实验/lab2/arwz_pace.ise_ISE_Backup
FPGA逻辑设计实验/lab2/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab2/kcpsm3.vhd
FPGA逻辑设计实验/lab2/kcuart_rx.vhd
FPGA逻辑设计实验/lab2/kcuart_tx.vhd
FPGA逻辑设计实验/lab2/uart_clock.vhd
FPGA逻辑设计实验/lab2/uart_clock_summary.html
FPGA逻辑设计实验/lab2/uart_rx.vhd
FPGA逻辑设计实验/lab2/uart_tx.vhd
FPGA逻辑设计实验/lab2/UCLOCK.VHD
FPGA逻辑设计实验/lab2/_xmsgs/
FPGA逻辑设计实验/lab3/
FPGA逻辑设计实验/lab3/Assembler/
FPGA逻辑设计实验/lab3/Assembler/assemble.bat
FPGA逻辑设计实验/lab3/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab3/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab3/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab3/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab3/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab3/Assembler/program.psm
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab3/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab3/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab3/Assembler/ROM_form.v
FPGA逻辑设计实验/lab3/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab3/loopback.vhd
FPGA逻辑设计实验/lab3/testbench.vhd
FPGA逻辑设计实验/lab3/time_const/
FPGA逻辑设计实验/lab3/time_const/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab3/time_const/isim.hdlsourcefiles
FPGA逻辑设计实验/lab3/time_const/isim.log
FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/
FPGA逻辑设计实验/lab3/time_const/isim.tmp_save/_1
FPGA逻辑设计实验/lab3/time_const/isimwavedata.xwv
FPGA逻辑设计实验/lab3/time_const/kcpsm3.vhd
FPGA逻辑设计实验/lab3/time_const/kcuart_rx.vhd
FPGA逻辑设计实验/lab3/time_const/kcuart_tx.vhd
FPGA逻辑设计实验/lab3/time_const/loopback.vhd
FPGA逻辑设计实验/lab3/time_const/loopback_summary.html
FPGA逻辑设计实验/lab3/time_const/my_dcm.xaw
FPGA逻辑设计实验/lab3/time_const/Project.dhp
FPGA逻辑设计实验/lab3/time_const/time_const.dhp
FPGA逻辑设计实验/lab3/time_const/time_const.ise
FPGA逻辑设计实验/lab3/time_const/time_const.ise.old
FPGA逻辑设计实验/lab3/time_const/time_const.ise_8.1i_backup
FPGA逻辑设计实验/lab3/time_const/time_const.ise_ISE_Backup
FPGA逻辑设计实验/lab3/time_const/uart_rx.vhd
FPGA逻辑设计实验/lab3/time_const/uart_tx.vhd
FPGA逻辑设计实验/lab3/time_const/_xmsgs/
FPGA逻辑设计实验/lab3/time_const/_xmsgs/fuse.xmsgs
FPGA逻辑设计实验/lab3/time_const/_xmsgs/vhpcomp.xmsgs
FPGA逻辑设计实验/lab4/
FPGA逻辑设计实验/lab4/Assembler/
FPGA逻辑设计实验/lab4/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab4/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab4/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab4/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab4/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab4/Assembler/program.psm
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab4/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab4/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab4/Assembler/ROM_form.v
FPGA逻辑设计实验/lab4/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab4/synth_lab/
FPGA逻辑设计实验/lab4/synth_lab/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcpsm3.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcuart_rx.vhd
FPGA逻辑设计实验/lab4/synth_lab/kcuart_tx.vhd
FPGA逻辑设计实验/lab4/synth_lab/loopback.ucf
FPGA逻辑设计实验/lab4/synth_lab/loopback.ut
FPGA逻辑设计实验/lab4/synth_lab/loopback.vhd
FPGA逻辑设计实验/lab4/synth_lab/loopback_prev_built.ngd
FPGA逻辑设计实验/lab4/synth_lab/loopback_summary.html
FPGA逻辑设计实验/lab4/synth_lab/my_dcm.xaw
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ise_ISE_Backup
FPGA逻辑设计实验/lab4/synth_lab/synth_lab.ntrc_log
FPGA逻辑设计实验/lab4/synth_lab/testbench.vhd
FPGA逻辑设计实验/lab4/synth_lab/uart_rx.vhd
FPGA逻辑设计实验/lab4/synth_lab/uart_tx.vhd
FPGA逻辑设计实验/lab4/synth_lab/_impact.cmd
FPGA逻辑设计实验/lab4/synth_lab/_impact.log
FPGA逻辑设计实验/lab4/synth_lab/_xmsgs/
FPGA逻辑设计实验/lab5/
FPGA逻辑设计实验/lab5/Assembler/
FPGA逻辑设计实验/lab5/Assembler/CONSTANT.TXT
FPGA逻辑设计实验/lab5/Assembler/KCPSM3.EXE
FPGA逻辑设计实验/lab5/Assembler/LABELS.TXT
FPGA逻辑设计实验/lab5/Assembler/PASS1.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS2.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS3.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS4.DAT
FPGA逻辑设计实验/lab5/Assembler/PASS5.DAT
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.COE
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.DEC
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.FMT
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.HEX
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.LOG
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.M
FPGA逻辑设计实验/lab5/Assembler/program.psm
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.V
FPGA逻辑设计实验/lab5/Assembler/PROGRAM.VHD
FPGA逻辑设计实验/lab5/Assembler/ROM_form.coe
FPGA逻辑设计实验/lab5/Assembler/ROM_form.v
FPGA逻辑设计实验/lab5/Assembler/ROM_form.vhd
FPGA逻辑设计实验/lab5/coregen/
FPGA逻辑设计实验/lab5/coregen/bbfifo_16x8.vhd
FPGA逻辑设计实验/lab5/coregen/coregen.ise
FPGA逻辑设计实验/lab5/coregen/coregen.ise_ISE_Backup
FPGA逻辑设计实验/lab5/coregen/coregen_ise9migration.zip
FPGA逻辑设计实验/lab5/coregen/kcpsm3.vhd
FPGA逻辑设计实验/lab5/coregen/kcuart_rx.vhd
FPGA逻辑设计实验/lab5/coregen/kcuart_tx.vhd
FPGA逻辑设计实验/
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.