文件名称:tmu_sinegen
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- 上传时间:2014-07-17
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文件大小:242.86kb
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已下载:0次
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利用dsp中硬件加速模块tmu快速产生正弦波信号,这样可以节省大量的时间,加快处理器的运行速率。-Using the DSP hardware acceleration module in tmu quickly generate sine wave signal, so that you can save a lot of time, speed up the processor speed.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
tmu_sinegen/cpu01/ccs/.ccsproject
tmu_sinegen/cpu01/ccs/.cproject
tmu_sinegen/cpu01/ccs/.launches/tmu_sinegen_cpu01.launch
tmu_sinegen/cpu01/ccs/.project
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.cdt.codan.core.prefs
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.cdt.debug.core.prefs
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.core.resources.prefs
tmu_sinegen/cpu01/ccs/CPU1_RAM/ccsObjs.opt
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CodeStartBranch.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CpuTimers.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CpuTimers.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_DefaultISR.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_DefaultISR.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_GlobalVariableDefs.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_GlobalVariableDefs.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Gpio.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Gpio.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Ipc.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Ipc.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieCtrl.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieCtrl.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieVect.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieVect.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_SysCtrl.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_SysCtrl.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_usDelay.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/makefile
tmu_sinegen/cpu01/ccs/CPU1_RAM/objects.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/sources.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/subdir_rules.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/subdir_vars.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.map
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.out
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01_linkInfo.xml
tmu_sinegen/cpu01/ccs/SetupDebugEnv.js
tmu_sinegen/cpu01/ccs/tmu_vs_rts.graphProp
tmu_sinegen/cpu01/tmu_sinegen_cpu01.c
tmu_sinegen/cpu01/ccs/.launches
tmu_sinegen/cpu01/ccs/.settings
tmu_sinegen/cpu01/ccs/CPU1_RAM
tmu_sinegen/cpu01/ccs
tmu_sinegen/cpu01
tmu_sinegen
tmu_sinegen/cpu01/ccs/.cproject
tmu_sinegen/cpu01/ccs/.launches/tmu_sinegen_cpu01.launch
tmu_sinegen/cpu01/ccs/.project
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.cdt.codan.core.prefs
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.cdt.debug.core.prefs
tmu_sinegen/cpu01/ccs/.settings/org.eclipse.core.resources.prefs
tmu_sinegen/cpu01/ccs/CPU1_RAM/ccsObjs.opt
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CodeStartBranch.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CpuTimers.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_CpuTimers.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_DefaultISR.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_DefaultISR.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_GlobalVariableDefs.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_GlobalVariableDefs.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Gpio.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Gpio.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Ipc.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_Ipc.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieCtrl.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieCtrl.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieVect.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_PieVect.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_SysCtrl.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_SysCtrl.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/F2837xD_usDelay.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/makefile
tmu_sinegen/cpu01/ccs/CPU1_RAM/objects.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/sources.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/subdir_rules.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/subdir_vars.mk
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.map
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.obj
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.out
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01.pp
tmu_sinegen/cpu01/ccs/CPU1_RAM/tmu_sinegen_cpu01_linkInfo.xml
tmu_sinegen/cpu01/ccs/SetupDebugEnv.js
tmu_sinegen/cpu01/ccs/tmu_vs_rts.graphProp
tmu_sinegen/cpu01/tmu_sinegen_cpu01.c
tmu_sinegen/cpu01/ccs/.launches
tmu_sinegen/cpu01/ccs/.settings
tmu_sinegen/cpu01/ccs/CPU1_RAM
tmu_sinegen/cpu01/ccs
tmu_sinegen/cpu01
tmu_sinegen
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