UART_DMA/.sopc_builder/filters.xml
UART_DMA/.sopc_builder/install.ptf
UART_DMA/.sopc_builder/install2.ptf
UART_DMA/.sopc_builder/preferences.xml
UART_DMA/altpllpll.ppf
UART_DMA/altpllpll.qip
UART_DMA/altpllpll.v
UART_DMA/altpllpll_0.ppf
UART_DMA/altpllpll_0.qip
UART_DMA/altpllpll_0.v
UART_DMA/altpllpll_0_wave0.jpg
UART_DMA/altpllpll_0_waveforms.html
UART_DMA/AUDIO_IF_0.v
UART_DMA/cpu_0.ocp
UART_DMA/cpu_0.sdc
UART_DMA/cpu_0.v
UART_DMA/cpu_0_bht_ram.mif
UART_DMA/cpu_0_dc_tag_ram.mif
UART_DMA/cpu_0_ic_tag_ram.mif
UART_DMA/cpu_0_jtag_debug_module_sysclk.v
UART_DMA/cpu_0_jtag_debug_module_tck.v
UART_DMA/cpu_0_jtag_debug_module_wrapper.v
UART_DMA/cpu_0_mult_cell.v
UART_DMA/cpu_0_ociram_default_contents.mif
UART_DMA/cpu_0_oci_test_bench.v
UART_DMA/cpu_0_rf_ram_a.mif
UART_DMA/cpu_0_rf_ram_b.mif
UART_DMA/cpu_0_test_bench.v
UART_DMA/db/UART_DMA.db_info
UART_DMA/db/UART_DMA.eco.cdb
UART_DMA/db/UART_DMA.sld_design_entry.sci
UART_DMA/DM9000A_IF_0.v
UART_DMA/dma_0.v
UART_DMA/DMA_SYSTEM.bsf
UART_DMA/DMA_SYSTEM.html
UART_DMA/DMA_SYSTEM.ptf
UART_DMA/DMA_SYSTEM.ptf.8.0
UART_DMA/DMA_SYSTEM.ptf.bak
UART_DMA/DMA_SYSTEM.ptf.pre_generation_ptf
UART_DMA/DMA_SYSTEM.qip
UART_DMA/DMA_SYSTEM.sopc
UART_DMA/DMA_SYSTEM.sopcinfo
UART_DMA/DMA_SYSTEM.v
UART_DMA/DMA_SYSTEM_clock_0.v
UART_DMA/DMA_SYSTEM_clock_1.v
UART_DMA/DMA_SYSTEM_clock_2.v
UART_DMA/DMA_SYSTEM_clock_3.v
UART_DMA/DMA_SYSTEM_clock_4.v
UART_DMA/DMA_SYSTEM_clock_5.v
UART_DMA/DMA_SYSTEM_clock_6.v
UART_DMA/DMA_SYSTEM_clock_7.v
UART_DMA/DMA_SYSTEM_generation_script
UART_DMA/DMA_SYSTEM_inst.v
UART_DMA/DMA_SYSTEM_log.txt
UART_DMA/DMA_SYSTEM_sim/atail-f.pl
UART_DMA/DMA_SYSTEM_sim/jtag_uart_0_input_mutex.dat
UART_DMA/DMA_SYSTEM_sim/jtag_uart_0_input_stream.dat
UART_DMA/DMA_SYSTEM_sim/jtag_uart_0_output_stream.dat
UART_DMA/DMA_SYSTEM_sim/uart_0_input_data_mutex.dat
UART_DMA/DMA_SYSTEM_sim/uart_0_input_data_stream.dat
UART_DMA/DMA_SYSTEM_sim/uart_0_log_module.txt
UART_DMA/epcs_flash_controller_0.v
UART_DMA/epcs_flash_controller_0_boot_rom.hex
UART_DMA/IP/TERASIC_AUDIO/hdl/AUDIO_ADC.v
UART_DMA/IP/TERASIC_AUDIO/hdl/AUDIO_DAC.v
UART_DMA/IP/TERASIC_AUDIO/hdl/audio_fifo.v
UART_DMA/IP/TERASIC_AUDIO/hdl/audio_fifo_wave0.jpg
UART_DMA/IP/TERASIC_AUDIO/hdl/audio_fifo_wave1.jpg
UART_DMA/IP/TERASIC_AUDIO/hdl/audio_fifo_waveforms.html
UART_DMA/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v
UART_DMA/IP/TERASIC_AUDIO/hdl/AUDIO_IF.v.bak
UART_DMA/IP/TERASIC_AUDIO/hdl/AUDIO_IF_hw.tcl
UART_DMA/IP/TERASIC_AUDIO/software/AUDIO.c
UART_DMA/IP/TERASIC_AUDIO/software/AUDIO.h
UART_DMA/IP/TERASIC_AUDIO/software/AUDIO_REG.h
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/Binary_VGA_Control_IF_hw.tcl~
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/Img_DATA.hex
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/Img_RAM.v
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Controller.v
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_NIOS_CTRL.v.bak
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_OSD_RAM.v
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl/VGA_Param.h
UART_DMA/IP/TERASIC_DM9000A/hdl/DM9000A_IF.v
UART_DMA/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl
UART_DMA/IP/TERASIC_DM9000A/hdl/DM9000A_IF_hw.tcl~
UART_DMA/IP/TERASIC_DM9000A/software/DM9000A.C
UART_DMA/IP/TERASIC_DM9000A/software/DM9000A.H
UART_DMA/IP/TERASIC_ISP1362/hdl/ISP1362_IF.v
UART_DMA/IP/TERASIC_ISP1362/hdl/ISP1362_IF_hw.tcl
UART_DMA/IP/TERASIC_SEG7/hdl/SEG7_IF.v
UART_DMA/IP/TERASIC_SEG7/hdl/SEG7_IF_hw.tcl
UART_DMA/IP/TERASIC_SEG7/software/SEG7.c
UART_DMA/IP/TERASIC_SEG7/software/SEG7.h
UART_DMA/ISP1362_IF_0.v
UART_DMA/jtag_uart_0.v
UART_DMA/onchip_memory2_0.hex
UART_DMA/onchip_memory2_0.v
UART_DMA/pio_button.v
UART_DMA/pio_LEDG.v
UART_DMA/pio_LEDR.v
UART_DMA/pio_switch.v
UART_DMA/pll.sdc
UART_DMA/pll.v
UART_DMA/sdram_0.v
UART_DMA/sdram_0_test_component.v
UART_DMA/sdram_u1.v
UART_DMA/sdram_u1_test_component.v
UART_DMA/sdram_u2.v
UART_DMA/sdram_u2_test_component.v
UART_DMA/SEG7_IF_0.v
UART_DMA/sopc_add_qip_file.tcl
UART_DMA/sopc_builder_log.txt
UART_DMA/timer_0.v
UART_DMA/uart_0.v
UART_DMA/UART_DMA.bdf
UART_DMA/UART_DMA.qpf
UART_DMA/UART_DMA.qsf
UART_DMA/UART_DMA.qws
UART_DMA/UART_DMA.v
UART_DMA/VGA_NIOS_CTRL_0.v
UART_DMA/IP/TERASIC_AUDIO/hdl
UART_DMA/IP/TERASIC_AUDIO/software
UART_DMA/IP/TERASIC_Binary_VGA_Controller/hdl
UART_DMA/IP/TERASIC_Binary_VGA_Controller/software
UART_DMA/IP/TERASIC_DM9000A/hdl
UART_DMA/IP/TERASIC_DM9000A/software
UART_DMA/IP/TERASIC_ISP1362/hdl
UART_DMA/IP/TERASIC_ISP1362/software
UART_DMA/IP/TERASIC_SEG7/hdl
UART_DMA/IP/TERASIC_SEG7/software
UART_DMA/IP/TERASIC_AUDIO
UART_DMA/IP/TERASIC_Binary_VGA_Controller
UART_DMA/IP/TERASIC_DM9000A
UART_DMA/IP/TERASIC_ISP1362
UART_DMA/IP/TERASIC_SEG7
UART_DMA/.sopc_builder
UART_DMA/db
UART_DMA/DMA_SYSTEM_sim
UART_DMA/IP
UART_DMA