文件名称:RISC_CPU
-
所属分类:
- 标签属性:
- 上传时间:2015-05-20
-
文件大小:341.62kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
RISC cpu设计,verilog语言,PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RISC_CPU/pre_sim/alu.v
RISC_CPU/pre_sim/alu.v.bak
RISC_CPU/pre_sim/clk_gen.v
RISC_CPU/pre_sim/cpu_top.v
RISC_CPU/pre_sim/data_ram.v
RISC_CPU/pre_sim/data_ram.v.bak
RISC_CPU/pre_sim/pc_cnt.v
RISC_CPU/pre_sim/pc_cnt.v.bak
RISC_CPU/pre_sim/pc_rom.v
RISC_CPU/pre_sim/pc_rom.v.bak
RISC_CPU/pre_sim/register.v
RISC_CPU/pre_sim/risc_cpu.cr.mti
RISC_CPU/pre_sim/risc_cpu.mpf
RISC_CPU/pre_sim/risc_cpu.v
RISC_CPU/pre_sim/vsim.wlf
RISC_CPU/pre_sim/work/_info
RISC_CPU/pre_sim/work/_vmake
RISC_CPU/pre_sim/work/_temp/vlog0gfn2g
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/verilog.asm
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/verilog.rw
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.dat
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.dbs
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.vhd
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/verilog.asm
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/verilog.rw
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.dat
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.dbs
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.vhd
RISC_CPU/pre_sim/work/@p@c_@r@o@m/verilog.asm
RISC_CPU/pre_sim/work/@p@c_@r@o@m/verilog.rw
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.dat
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.dbs
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.vhd
RISC_CPU/pre_sim/work/@p@c_@c@n@t/verilog.asm
RISC_CPU/pre_sim/work/@p@c_@c@n@t/verilog.rw
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.dat
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.dbs
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.vhd
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/verilog.asm
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/verilog.rw
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.dat
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.dbs
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.vhd
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/verilog.asm
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/verilog.rw
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.dat
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.dbs
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.vhd
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/verilog.asm
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/verilog.rw
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.dat
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.dbs
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.vhd
RISC_CPU/pre_sim/work/@a@l@u/verilog.asm
RISC_CPU/pre_sim/work/@a@l@u/verilog.rw
RISC_CPU/pre_sim/work/@a@l@u/_primary.dat
RISC_CPU/pre_sim/work/@a@l@u/_primary.dbs
RISC_CPU/pre_sim/work/@a@l@u/_primary.vhd
RISC_CPU/pre_sim/report/report.txt
RISC_CPU/post_sim/cpu_top.v
RISC_CPU/post_sim/risc_cpu.sdf
RISC_CPU/post_sim/risc_cpu_netlist.v
RISC_CPU/dc/command.log
RISC_CPU/dc/default.svf
RISC_CPU/dc/filenames.log
RISC_CPU/dc/risc_cpu.sdf
RISC_CPU/dc/risc_cpu_netlist.v
RISC_CPU/dc/verilog/alu.v
RISC_CPU/dc/verilog/clk_gen.v
RISC_CPU/dc/verilog/cpu_top.v
RISC_CPU/dc/verilog/data_ram.v
RISC_CPU/dc/verilog/pc_cnt.v
RISC_CPU/dc/verilog/pc_rom.v
RISC_CPU/dc/verilog/register.v
RISC_CPU/dc/verilog/risc_cpu.v
RISC_CPU/dc/verilog/transcript
RISC_CPU/dc/report/area.txt
RISC_CPU/dc/report/constraint.txt
RISC_CPU/dc/report/timing.txt
RISC_CPU/dc/ddc/ALU.ddc
RISC_CPU/dc/ddc/ALU_DW01_add_0.ddc
RISC_CPU/dc/ddc/ALU_DW01_add_1.ddc
RISC_CPU/dc/ddc/ALU_DW01_inc_0.ddc
RISC_CPU/dc/ddc/ALU_DW01_sub_0.ddc
RISC_CPU/dc/ddc/CLK_GEN.ddc
RISC_CPU/dc/ddc/jizheshanchu.db.ddc
RISC_CPU/dc/ddc/PC_CNT.ddc
RISC_CPU/dc/ddc/PC_CNT_DW01_inc_0.ddc
RISC_CPU/dc/ddc/PC_CNT_DW01_inc_1.ddc
RISC_CPU/dc/ddc/REGISTER.ddc
RISC_CPU/dc/ddc/RISC_CPU.ddc
RISC_CPU/pre_sim/work/_temp
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r
RISC_CPU/pre_sim/work/@p@c_@r@o@m
RISC_CPU/pre_sim/work/@p@c_@c@n@t
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n
RISC_CPU/pre_sim/work/@a@l@u
RISC_CPU/pre_sim/work
RISC_CPU/pre_sim/report
RISC_CPU/dc/verilog
RISC_CPU/dc/report
RISC_CPU/dc/ddc
RISC_CPU/pre_sim
RISC_CPU/post_sim
RISC_CPU/dc
RISC_CPU
RISC_CPU/pre_sim/alu.v.bak
RISC_CPU/pre_sim/clk_gen.v
RISC_CPU/pre_sim/cpu_top.v
RISC_CPU/pre_sim/data_ram.v
RISC_CPU/pre_sim/data_ram.v.bak
RISC_CPU/pre_sim/pc_cnt.v
RISC_CPU/pre_sim/pc_cnt.v.bak
RISC_CPU/pre_sim/pc_rom.v
RISC_CPU/pre_sim/pc_rom.v.bak
RISC_CPU/pre_sim/register.v
RISC_CPU/pre_sim/risc_cpu.cr.mti
RISC_CPU/pre_sim/risc_cpu.mpf
RISC_CPU/pre_sim/risc_cpu.v
RISC_CPU/pre_sim/vsim.wlf
RISC_CPU/pre_sim/work/_info
RISC_CPU/pre_sim/work/_vmake
RISC_CPU/pre_sim/work/_temp/vlog0gfn2g
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/verilog.asm
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/verilog.rw
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.dat
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.dbs
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u/_primary.vhd
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/verilog.asm
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/verilog.rw
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.dat
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.dbs
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r/_primary.vhd
RISC_CPU/pre_sim/work/@p@c_@r@o@m/verilog.asm
RISC_CPU/pre_sim/work/@p@c_@r@o@m/verilog.rw
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.dat
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.dbs
RISC_CPU/pre_sim/work/@p@c_@r@o@m/_primary.vhd
RISC_CPU/pre_sim/work/@p@c_@c@n@t/verilog.asm
RISC_CPU/pre_sim/work/@p@c_@c@n@t/verilog.rw
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.dat
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.dbs
RISC_CPU/pre_sim/work/@p@c_@c@n@t/_primary.vhd
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/verilog.asm
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/verilog.rw
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.dat
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.dbs
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m/_primary.vhd
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/verilog.asm
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/verilog.rw
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.dat
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.dbs
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p/_primary.vhd
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/verilog.asm
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/verilog.rw
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.dat
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.dbs
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n/_primary.vhd
RISC_CPU/pre_sim/work/@a@l@u/verilog.asm
RISC_CPU/pre_sim/work/@a@l@u/verilog.rw
RISC_CPU/pre_sim/work/@a@l@u/_primary.dat
RISC_CPU/pre_sim/work/@a@l@u/_primary.dbs
RISC_CPU/pre_sim/work/@a@l@u/_primary.vhd
RISC_CPU/pre_sim/report/report.txt
RISC_CPU/post_sim/cpu_top.v
RISC_CPU/post_sim/risc_cpu.sdf
RISC_CPU/post_sim/risc_cpu_netlist.v
RISC_CPU/dc/command.log
RISC_CPU/dc/default.svf
RISC_CPU/dc/filenames.log
RISC_CPU/dc/risc_cpu.sdf
RISC_CPU/dc/risc_cpu_netlist.v
RISC_CPU/dc/verilog/alu.v
RISC_CPU/dc/verilog/clk_gen.v
RISC_CPU/dc/verilog/cpu_top.v
RISC_CPU/dc/verilog/data_ram.v
RISC_CPU/dc/verilog/pc_cnt.v
RISC_CPU/dc/verilog/pc_rom.v
RISC_CPU/dc/verilog/register.v
RISC_CPU/dc/verilog/risc_cpu.v
RISC_CPU/dc/verilog/transcript
RISC_CPU/dc/report/area.txt
RISC_CPU/dc/report/constraint.txt
RISC_CPU/dc/report/timing.txt
RISC_CPU/dc/ddc/ALU.ddc
RISC_CPU/dc/ddc/ALU_DW01_add_0.ddc
RISC_CPU/dc/ddc/ALU_DW01_add_1.ddc
RISC_CPU/dc/ddc/ALU_DW01_inc_0.ddc
RISC_CPU/dc/ddc/ALU_DW01_sub_0.ddc
RISC_CPU/dc/ddc/CLK_GEN.ddc
RISC_CPU/dc/ddc/jizheshanchu.db.ddc
RISC_CPU/dc/ddc/PC_CNT.ddc
RISC_CPU/dc/ddc/PC_CNT_DW01_inc_0.ddc
RISC_CPU/dc/ddc/PC_CNT_DW01_inc_1.ddc
RISC_CPU/dc/ddc/REGISTER.ddc
RISC_CPU/dc/ddc/RISC_CPU.ddc
RISC_CPU/pre_sim/work/_temp
RISC_CPU/pre_sim/work/@r@i@s@c_@c@p@u
RISC_CPU/pre_sim/work/@r@e@g@i@s@t@e@r
RISC_CPU/pre_sim/work/@p@c_@r@o@m
RISC_CPU/pre_sim/work/@p@c_@c@n@t
RISC_CPU/pre_sim/work/@d@a@t@a_@r@a@m
RISC_CPU/pre_sim/work/@c@p@u_@t@o@p
RISC_CPU/pre_sim/work/@c@l@k_@g@e@n
RISC_CPU/pre_sim/work/@a@l@u
RISC_CPU/pre_sim/work
RISC_CPU/pre_sim/report
RISC_CPU/dc/verilog
RISC_CPU/dc/report
RISC_CPU/dc/ddc
RISC_CPU/pre_sim
RISC_CPU/post_sim
RISC_CPU/dc
RISC_CPU
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.