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文件名称:1602-display-char

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2015-10-31
  • 文件大小：
    2.45mb
  • 已下载：
    0次
  • 提 供 者：
    刘***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这是lcd1602的显示字符的Verilog源代码，经过测试可用，便于读者学习。-This is the LCD1602 of the Verilog source code, after testing can be used to facilitate the reader to learn.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

1602 display char/db/
1602 display char/db/add_sub_lkc.tdf
1602 display char/db/add_sub_mkc.tdf
1602 display char/db/alt_u_div_ive.tdf
1602 display char/db/alt_u_div_kve.tdf
1602 display char/db/lcd1602.db_info
1602 display char/db/lcd1602.sld_design_entry.sci
1602 display char/db/logic_util_heursitic.dat
1602 display char/db/lpm_divide_15m.tdf
1602 display char/db/lpm_divide_25m.tdf
1602 display char/db/lpm_divide_ucm.tdf
1602 display char/db/lpm_divide_vcm.tdf
1602 display char/db/prev_cmp_lcd1602.qmsg
1602 display char/db/sign_div_unsign_8kh.tdf
1602 display char/db/sign_div_unsign_9kh.tdf
1602 display char/incremental_db/
1602 display char/incremental_db/compiled_partitions/
1602 display char/incremental_db/compiled_partitions/lcd1602.db_info
1602 display char/incremental_db/compiled_partitions/lcd1602.root_partition.cmp.dfp
1602 display char/incremental_db/compiled_partitions/lcd1602.root_partition.cmp.kpt
1602 display char/incremental_db/compiled_partitions/lcd1602.root_partition.cmp.logdb
1602 display char/incremental_db/compiled_partitions/lcd1602.root_partition.map.dpi
1602 display char/incremental_db/compiled_partitions/lcd1602.root_partition.map.kpt
1602 display char/incremental_db/README
1602 display char/lcd1602.asm.rpt
1602 display char/lcd1602.cdf
1602 display char/lcd1602.done
1602 display char/lcd1602.eda.rpt
1602 display char/lcd1602.fit.rpt
1602 display char/lcd1602.fit.smsg
1602 display char/lcd1602.fit.summary
1602 display char/lcd1602.flow.rpt
1602 display char/lcd1602.map.rpt
1602 display char/lcd1602.map.smsg
1602 display char/lcd1602.map.summary
1602 display char/lcd1602.pin
1602 display char/lcd1602.pof
1602 display char/lcd1602.qpf
1602 display char/lcd1602.qsf
1602 display char/lcd1602.sof
1602 display char/lcd1602.sta.rpt
1602 display char/lcd1602.sta.summary
1602 display char/lcd1602.v
1602 display char/lcd1602.v.bak
1602 display char/lcd1602_assignment_defaults.qdf
1602 display char/lcd1602_nativelink_simulation.rpt
1602 display char/simulation/
1602 display char/simulation/modelsim/
1602 display char/simulation/modelsim/gate_work/
1602 display char/simulation/modelsim/gate_work/_info
1602 display char/simulation/modelsim/gate_work/_temp/
1602 display char/simulation/modelsim/gate_work/_vmake
1602 display char/simulation/modelsim/gate_work/lcd1602/
1602 display char/simulation/modelsim/gate_work/lcd1602/_primary.dat
1602 display char/simulation/modelsim/gate_work/lcd1602/_primary.dbs
1602 display char/simulation/modelsim/gate_work/lcd1602/_primary.vhd
1602 display char/simulation/modelsim/gate_work/lcd1602/verilog.prw
1602 display char/simulation/modelsim/gate_work/lcd1602/verilog.psm
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/_primary.dat
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/_primary.dbs
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/_primary.vhd
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/verilog.prw
1602 display char/simulation/modelsim/gate_work/lcd1602_vlg_tst/verilog.psm
1602 display char/simulation/modelsim/lcd1602.sft
1602 display char/simulation/modelsim/lcd1602.vo
1602 display char/simulation/modelsim/lcd1602.vt
1602 display char/simulation/modelsim/lcd1602.vt.bak
1602 display char/simulation/modelsim/lcd1602_fast.vo
1602 display char/simulation/modelsim/lcd1602_modelsim.xrf
1602 display char/simulation/modelsim/lcd1602_run_msim_gate_verilog.do
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do.bak
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do.bak1
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do.bak2
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do.bak3
1602 display char/simulation/modelsim/lcd1602_run_msim_rtl_verilog.do.bak4
1602 display char/simulation/modelsim/lcd1602_v.sdo
1602 display char/simulation/modelsim/lcd1602_v.sdo_typ.csd
1602 display char/simulation/modelsim/lcd1602_v_fast.sdo
1602 display char/simulation/modelsim/msim_transcript
1602 display char/simulation/modelsim/rtl_work/
1602 display char/simulation/modelsim/rtl_work/_info
1602 display char/simulation/modelsim/rtl_work/_temp/
1602 display char/simulation/modelsim/rtl_work/_vmake
1602 display char/simulation/modelsim/rtl_work/lcd1602/
1602 display char/simulation/modelsim/rtl_work/lcd1602/_primary.dat
1602 display char/simulation/modelsim/rtl_work/lcd1602/_primary.dbs
1602 display char/simulation/modelsim/rtl_work/lcd1602/_primary.vhd
1602 display char/simulation/modelsim/rtl_work/lcd1602/verilog.prw
1602 display char/simulation/modelsim/rtl_work/lcd1602/verilog.psm
1602 display char/simulation/modelsim/rtl_work/lcd1602_vlg_tst/
1602 display char/simulation/modelsim/rtl_work/lcd1602_vlg_tst/_primary.dat
1602 display char/simulation/modelsim/rtl_work/lcd1602_vlg_tst/_primary.dbs
1602 display char/simulation/modelsim/rtl_work/lcd1602_vlg_tst/_primary.vhd
1602 display char/simulation/modelsim/rtl_work/lcd1602_vlg_tst

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