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文件名称:bt-master

  • 所属分类：
    Windows Develop
  • 标签属性：
    [PDF]
  • 上传时间：
    2015-11-29
  • 文件大小：
    14.52mb
  • 已下载：
    0次
  • 提 供 者：
    vhdl*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

ADC and DAC interface for bt tracker -this code is used to do bt tracker project
(系统自动生成,下载前可以参看下载内容)

下载文件列表

bt-master/
bt-master/.gitignore
bt-master/README.md
bt-master/bsv/
bt-master/bsv/BeatClassifier.bsv
bt-master/bsv/BeatTracker.bsv
bt-master/bsv/FIRFilter.bsv
bt-master/bsv/Metronome.bsv
bt-master/bsv/Types.bsv
bt-master/doc/
bt-master/doc/01-prelim-proposal/
bt-master/doc/01-prelim-proposal/fig/
bt-master/doc/01-prelim-proposal/fig/architecture.pdf
bt-master/doc/01-prelim-proposal/fig/architecture.svg
bt-master/doc/01-prelim-proposal/fig/implementation.pdf
bt-master/doc/01-prelim-proposal/fig/implementation.svg
bt-master/doc/01-prelim-proposal/fig/swscreenshot.png
bt-master/doc/01-prelim-proposal/render.sh
bt-master/doc/01-prelim-proposal/tex/
bt-master/doc/01-prelim-proposal/tex/main.tex
bt-master/doc/02-idea-presentation/
bt-master/doc/02-idea-presentation/fig/
bt-master/doc/02-idea-presentation/fig/architecture.pdf
bt-master/doc/02-idea-presentation/fig/architecture.svg
bt-master/doc/02-idea-presentation/fig/implementation.pdf
bt-master/doc/02-idea-presentation/fig/implementation.svg
bt-master/doc/02-idea-presentation/fig/target.pdf
bt-master/doc/02-idea-presentation/fig/target.svg
bt-master/doc/02-idea-presentation/render.sh
bt-master/doc/02-idea-presentation/tex/
bt-master/doc/02-idea-presentation/tex/main.tex
bt-master/doc/03-final-proposal/
bt-master/doc/03-final-proposal/fig/
bt-master/doc/03-final-proposal/fig/architecture.pdf
bt-master/doc/03-final-proposal/fig/architecture.svg
bt-master/doc/03-final-proposal/fig/implementation.pdf
bt-master/doc/03-final-proposal/fig/implementation.svg
bt-master/doc/03-final-proposal/fig/swscreenshot.png
bt-master/doc/03-final-proposal/render.sh
bt-master/doc/03-final-proposal/tex/
bt-master/doc/03-final-proposal/tex/main.tex
bt-master/doc/04-microarchitecture/
bt-master/doc/04-microarchitecture/fig/
bt-master/doc/04-microarchitecture/fig/architecture.pdf
bt-master/doc/04-microarchitecture/fig/architecture.svg
bt-master/doc/04-microarchitecture/fig/implementation.pdf
bt-master/doc/04-microarchitecture/fig/implementation.svg
bt-master/doc/04-microarchitecture/fig/swscreenshot.png
bt-master/doc/04-microarchitecture/render.sh
bt-master/doc/04-microarchitecture/tex/
bt-master/doc/04-microarchitecture/tex/main.tex
bt-master/doc/05-implementation-status/
bt-master/doc/05-implementation-status/fig/
bt-master/doc/05-implementation-status/fig/architecture.pdf
bt-master/doc/05-implementation-status/fig/architecture.svg
bt-master/doc/05-implementation-status/fig/implementation.pdf
bt-master/doc/05-implementation-status/fig/implementation.svg
bt-master/doc/05-implementation-status/fig/swscreenshot.png
bt-master/doc/05-implementation-status/render.sh
bt-master/doc/05-implementation-status/tex/
bt-master/doc/05-implementation-status/tex/main.tex
bt-master/doc/06-prelim-synthesis/
bt-master/doc/06-prelim-synthesis/render.sh
bt-master/doc/06-prelim-synthesis/tex/
bt-master/doc/06-prelim-synthesis/tex/main.tex
bt-master/doc/07-first-run/
bt-master/doc/07-first-run/fig/
bt-master/doc/07-first-run/fig/swscreenshot.png
bt-master/doc/07-first-run/render.sh
bt-master/doc/07-first-run/tex/
bt-master/doc/07-first-run/tex/main.tex
bt-master/doc/08-fpga-demo/
bt-master/doc/08-fpga-demo/render.sh
bt-master/doc/08-fpga-demo/tex/
bt-master/doc/08-fpga-demo/tex/main.tex
bt-master/doc/09-final-report/
bt-master/doc/09-final-report/fig/
bt-master/doc/09-final-report/fig/architecture.pdf
bt-master/doc/09-final-report/fig/architecture.svg
bt-master/doc/09-final-report/fig/dcbias.pdf
bt-master/doc/09-final-report/fig/dcbias.svg
bt-master/doc/09-final-report/fig/dcbiasbrd.jpg
bt-master/doc/09-final-report/fig/hwarch.pdf
bt-master/doc/09-final-report/fig/hwarch.svg
bt-master/doc/09-final-report/fig/setup-full.jpg
bt-master/doc/09-final-report/fig/setup.jpg
bt-master/doc/09-final-report/fig/swss.png
bt-master/doc/09-final-report/render.sh
bt-master/doc/09-final-report/tex/
bt-master/doc/09-final-report/tex/main.tex
bt-master/doc/10-final-presentation/
bt-master/doc/10-final-presentation/fig/
bt-master/doc/10-final-presentation/fig/architecture.pdf
bt-master/doc/10-final-presentation/fig/architecture.svg
bt-master/doc/10-final-presentation/fig/dcbias.pdf
bt-master/doc/10-final-presentation/fig/dcbias.svg
bt-master/doc/10-final-presentation/fig/dcbiasbrd.jpg
bt-master/doc/10-final-presentation/fig/hwarch.pdf
bt-master/doc/10-final-presentation/fig/hwarch.svg
bt-master/doc/10-final-presentation/fig/implementation.pdf
bt-master/doc/10-final-presentation/fig/implementation.svg
bt-master/doc/10-final-presentation/fig/setup.jpg
bt-master/doc/10-final-presentation/fig/target.pdf
bt-master/doc/10-final-presentation/fig/target.svg
bt-master/doc/10-final-presentation/render.sh
bt-master/doc/10-final-presentation/tex/
bt-master/doc/10-final-presentation/tex/main.tex
bt-master/doc/common/
bt-master/doc/common/tex/
bt-master/doc/common/tex/environment.tex
bt-master/fpga/
bt-master/fpga/bits/
bt-master/fpga/bits/13-05-10-working.bit
bt-master/fpga/bsc/
bt-master/fpga/bsc/Makefile
bt-master/fpga/bsc/bt.bspec
bt-master/fpga/bsc/mkBeatTracker.v
bt-master/fpga/build/
bt-master/fpga/build/build-xilinx.sh
bt-master/fpga/build/build.sh
bt-m

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