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文件名称:pll_prj

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    2016-01-23
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    125.58kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

PLL配置仿真实验

PLL,即锁相环。简单的理解,给PLL 一个时钟输入(一般是外部晶振时钟),

然后经过PLL 内部的处理以后,在PLL 的输出端口就可以得到一定范围的时钟频

率。其之所以应用广泛,因为从PLL 输出得到的时钟不仅仅从频率和相位上比较

稳定,而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
(系统自动生成,下载前可以参看下载内容)

下载文件列表

pll_prj/
pll_prj/db/
pll_prj/db/logic_util_heursitic.dat
pll_prj/db/pll_prj.db_info
pll_prj/db/pll_prj.sld_design_entry.sci
pll_prj/db/prev_cmp_pll_prj.eda.qmsg
pll_prj/db/prev_cmp_pll_prj.fit.qmsg
pll_prj/db/prev_cmp_pll_prj.map.qmsg
pll_prj/db/prev_cmp_pll_prj.qmsg
pll_prj/incremental_db/
pll_prj/incremental_db/README
pll_prj/incremental_db/compiled_partitions/
pll_prj/incremental_db/compiled_partitions/pll_prj.db_info
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.cmp.dfp
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.cmp.kpt
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.cmp.logdb
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.map.dpi
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.map.kpt
pll_prj/incremental_db/compiled_partitions/pll_prj.root_partition.merge_hb.atm
pll_prj/pll_ctrl.ppf
pll_prj/pll_ctrl.qip
pll_prj/pll_ctrl.v
pll_prj/pll_ctrl_bb.v
pll_prj/pll_ctrl_inst.v
pll_prj/pll_prj.asm.rpt
pll_prj/pll_prj.done
pll_prj/pll_prj.dpf
pll_prj/pll_prj.eda.rpt
pll_prj/pll_prj.fit.rpt
pll_prj/pll_prj.fit.summary
pll_prj/pll_prj.flow.rpt
pll_prj/pll_prj.map.rpt
pll_prj/pll_prj.map.summary
pll_prj/pll_prj.pin
pll_prj/pll_prj.pof
pll_prj/pll_prj.qpf
pll_prj/pll_prj.qsf
pll_prj/pll_prj.qws
pll_prj/pll_prj.sof
pll_prj/pll_prj.v
pll_prj/pll_prj_assignment_defaults.qdf
pll_prj/pll_prj_nativelink_simulation.rpt
pll_prj/simulation/
pll_prj/simulation/modelsim/
pll_prj/simulation/modelsim/modelsim.ini
pll_prj/simulation/modelsim/msim_transcript
pll_prj/simulation/modelsim/pll_prj.vt
pll_prj/simulation/modelsim/pll_prj_run_msim_rtl_verilog.do
pll_prj/simulation/modelsim/rtl_work/
pll_prj/simulation/modelsim/rtl_work/_info
pll_prj/simulation/modelsim/rtl_work/_temp/
pll_prj/simulation/modelsim/rtl_work/_vmake
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/_primary.dat
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/_primary.dbs
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/_primary.vhd
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/verilog.prw
pll_prj/simulation/modelsim/rtl_work/pll_ctrl/verilog.psm
pll_prj/simulation/modelsim/rtl_work/pll_prj/
pll_prj/simulation/modelsim/rtl_work/pll_prj/_primary.dat
pll_prj/simulation/modelsim/rtl_work/pll_prj/_primary.dbs
pll_prj/simulation/modelsim/rtl_work/pll_prj/_primary.vhd
pll_prj/simulation/modelsim/rtl_work/pll_prj/verilog.prw
pll_prj/simulation/modelsim/rtl_work/pll_prj/verilog.psm
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.dat
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.dbs
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/_primary.vhd
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/verilog.prw
pll_prj/simulation/modelsim/rtl_work/pll_prj_vlg_tst/verilog.psm
pll_prj/simulation/modelsim/vsim.wlf

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