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文件名称:uart

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2016-04-13
  • 文件大小：
    2.45mb
  • 已下载：
    0次
  • 提 供 者：
    杨***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

verilog 编写的FPGA串口报文收发程序，带奇偶校验位，并含有DS18B20温度传感器驱动程序，可以自行设置波特率.-verilog prepared by the FPGA serial transceiver procedures packets with parity, and contains a temperature sensor DS18B20 driver, you can set the baud rate yourself.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart/11.wcfg
uart/debug.cdc
uart/fuse.log
uart/fuse.xmsgs
uart/fuseRelaunch.cmd
uart/ipcore_dir/coregen.cgp
uart/ipcore_dir/coregen.log
uart/ipcore_dir/create_pll_clock.tcl
uart/ipcore_dir/edit_pll_clock.tcl
uart/ipcore_dir/pll_clock/clk_wiz_v3_6_readme.txt
uart/ipcore_dir/pll_clock/doc/clk_wiz_v3_6_readme.txt
uart/ipcore_dir/pll_clock/doc/clk_wiz_v3_6_vinfo.html
uart/ipcore_dir/pll_clock/doc/pg065_clk_wiz.pdf
uart/ipcore_dir/pll_clock/example_design/pll_clock_exdes.ucf
uart/ipcore_dir/pll_clock/example_design/pll_clock_exdes.v
uart/ipcore_dir/pll_clock/example_design/pll_clock_exdes.xdc
uart/ipcore_dir/pll_clock/implement/implement.bat
uart/ipcore_dir/pll_clock/implement/implement.sh
uart/ipcore_dir/pll_clock/implement/planAhead_ise.bat
uart/ipcore_dir/pll_clock/implement/planAhead_ise.sh
uart/ipcore_dir/pll_clock/implement/planAhead_ise.tcl
uart/ipcore_dir/pll_clock/implement/planAhead_rdn.bat
uart/ipcore_dir/pll_clock/implement/planAhead_rdn.sh
uart/ipcore_dir/pll_clock/implement/planAhead_rdn.tcl
uart/ipcore_dir/pll_clock/implement/xst.prj
uart/ipcore_dir/pll_clock/implement/xst.scr
uart/ipcore_dir/pll_clock/simulation/functional/simcmds.tcl
uart/ipcore_dir/pll_clock/simulation/functional/simulate_isim.bat
uart/ipcore_dir/pll_clock/simulation/functional/simulate_isim.sh
uart/ipcore_dir/pll_clock/simulation/functional/simulate_mti.bat
uart/ipcore_dir/pll_clock/simulation/functional/simulate_mti.do
uart/ipcore_dir/pll_clock/simulation/functional/simulate_mti.sh
uart/ipcore_dir/pll_clock/simulation/functional/simulate_ncsim.sh
uart/ipcore_dir/pll_clock/simulation/functional/simulate_vcs.sh
uart/ipcore_dir/pll_clock/simulation/functional/ucli_commands.key
uart/ipcore_dir/pll_clock/simulation/functional/vcs_session.tcl
uart/ipcore_dir/pll_clock/simulation/functional/wave.do
uart/ipcore_dir/pll_clock/simulation/functional/wave.sv
uart/ipcore_dir/pll_clock/simulation/pll_clock_tb.v
uart/ipcore_dir/pll_clock/simulation/timing/pll_clock_tb.v
uart/ipcore_dir/pll_clock/simulation/timing/sdf_cmd_file
uart/ipcore_dir/pll_clock/simulation/timing/simcmds.tcl
uart/ipcore_dir/pll_clock/simulation/timing/simulate_isim.sh
uart/ipcore_dir/pll_clock/simulation/timing/simulate_mti.bat
uart/ipcore_dir/pll_clock/simulation/timing/simulate_mti.do
uart/ipcore_dir/pll_clock/simulation/timing/simulate_mti.sh
uart/ipcore_dir/pll_clock/simulation/timing/simulate_ncsim.sh
uart/ipcore_dir/pll_clock/simulation/timing/simulate_vcs.sh
uart/ipcore_dir/pll_clock/simulation/timing/ucli_commands.key
uart/ipcore_dir/pll_clock/simulation/timing/vcs_session.tcl
uart/ipcore_dir/pll_clock/simulation/timing/wave.do
uart/ipcore_dir/pll_clock.asy
uart/ipcore_dir/pll_clock.gise
uart/ipcore_dir/pll_clock.ncf
uart/ipcore_dir/pll_clock.sym
uart/ipcore_dir/pll_clock.ucf
uart/ipcore_dir/pll_clock.v
uart/ipcore_dir/pll_clock.veo
uart/ipcore_dir/pll_clock.xco
uart/ipcore_dir/pll_clock.xdc
uart/ipcore_dir/pll_clock.xise
uart/ipcore_dir/pll_clock_flist.txt
uart/ipcore_dir/pll_clock_xmdf.tcl
uart/ipcore_dir/tmp/customization_gui.0.187136464374.out
uart/ipcore_dir/tmp/customization_gui.0.520778292101.out
uart/ipcore_dir/tmp/customization_gui.0.963496225869.out
uart/ipcore_dir/tmp/_cg/_dbg/xil_379.in
uart/ipcore_dir/tmp/_cg/_dbg/xil_379.out
uart/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
uart/ipcore_dir/_xmsgs/cg.xmsgs
uart/ipcore_dir/_xmsgs/pn_parser.xmsgs
uart/iseconfig/RX_QD.xreport
uart/iseconfig/uar.projectmgr
uart/isim/isim_usage_statistics.html
uart/isim/pn_info
uart/isim/temp/@c@l@k_@d@i@v.sdb
uart/isim/temp/cmd_reply.sdb
uart/isim/temp/creat_cmd.sdb
uart/isim/temp/glbl.sdb
uart/isim/temp/uart_rx_1byte.sdb
uart/isim/temp/uart_top.sdb
uart/isim/temp/uart_top_tb.sdb
uart/isim/temp/uart_tx_1byte.sdb
uart/isim/uart_top_isim_beh.exe.sim/isimcrash.log
uart/isim/uart_top_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
uart/isim/uart_top_isim_beh.exe.sim/isimkernel.log
uart/isim/uart_top_isim_beh.exe.sim/libPortability.dll
uart/isim/uart_top_isim_beh.exe.sim/netId.dat
uart/isim/uart_top_isim_beh.exe.sim/tmp_save/_1
uart/isim/uart_top_isim_beh.exe.sim/uart_top_isim_beh.exe
uart/isim/uart_top_isim_beh.exe.sim/unisims_ver/m_00000000003266096158_2593380106.c
uart/isim/uart_top_isim_beh.exe.sim/unisims_ver/m_00000000003266096158_2593380106.didat
uart/isim/uart_top_isim_beh.exe.sim/unisims_ver/m_00000000003266096158_2593380106.nt64.obj
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000405549347_0990403961.c
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000405549347_0990403961.didat
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000405549347_0990403961.nt64.obj
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000809211706_1273538878.c
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000809211706_1273538878.didat
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000000809211706_1273538878.nt64.obj
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000002842791829_2374475961.c
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000002842791829_2374475961.didat
uart/isim/uart_top_isim_beh.exe.sim/work/m_00000000002842791829_2374475961.nt64.obj
uart/isim/uart_top_isim_beh.exe.sim/work/m_

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