文件名称:S6_VHDLproject
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- 上传时间:2016-05-24
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文件大小:2.45mb
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常用的VHDL模块,适合VHDL入门者,本系列一共包含六个VHDL模块,本模块是计算机运算器模块(S6)实现运算器相关功能
1.算术逻辑单元(alu_1706),实现算术逻辑运算
2.CPU寄存器组(cpu_register),实现四个通用寄存器(具有读写功能),一个PC寄存器(清零,置数,加一计数,减一计数,工作使能)。
3.全加器(full_adder)
4.半加器(half_adder)
5.3-8译码器(mutex_3to8)
6.计算机运算器(S6)实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
1.算术逻辑单元(alu_1706),实现算术逻辑运算
2.CPU寄存器组(cpu_register),实现四个通用寄存器(具有读写功能),一个PC寄存器(清零,置数,加一计数,减一计数,工作使能)。
3.全加器(full_adder)
4.半加器(half_adder)
5.3-8译码器(mutex_3to8)
6.计算机运算器(S6)实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
(系统自动生成,下载前可以参看下载内容)
下载文件列表
S6【VHDLproject】/ALU_8.bsf
S6【VHDLproject】/ALU_8.vhd
S6【VHDLproject】/ALU_8.vhd.bak
S6【VHDLproject】/CPU_8.bsf
S6【VHDLproject】/CPU_8.vhd
S6【VHDLproject】/CPU_8.vhd.bak
S6【VHDLproject】/db/logic_util_heursitic.dat
S6【VHDLproject】/db/prev_cmp_YSQ_8.qmsg
S6【VHDLproject】/db/YSQ_8.(0).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(0).cnf.hdb
S6【VHDLproject】/db/YSQ_8.(1).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(1).cnf.hdb
S6【VHDLproject】/db/YSQ_8.(2).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(2).cnf.hdb
S6【VHDLproject】/db/YSQ_8.asm.qmsg
S6【VHDLproject】/db/YSQ_8.asm.rdb
S6【VHDLproject】/db/YSQ_8.asm_labs.ddb
S6【VHDLproject】/db/YSQ_8.cbx.xml
S6【VHDLproject】/db/YSQ_8.cmp.bpm
S6【VHDLproject】/db/YSQ_8.cmp.cdb
S6【VHDLproject】/db/YSQ_8.cmp.hdb
S6【VHDLproject】/db/YSQ_8.cmp.idb
S6【VHDLproject】/db/YSQ_8.cmp.kpt
S6【VHDLproject】/db/YSQ_8.cmp.logdb
S6【VHDLproject】/db/YSQ_8.cmp.rdb
S6【VHDLproject】/db/YSQ_8.cmp_merge.kpt
S6【VHDLproject】/db/YSQ_8.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
S6【VHDLproject】/db/YSQ_8.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
S6【VHDLproject】/db/YSQ_8.db_info
S6【VHDLproject】/db/YSQ_8.eda.qmsg
S6【VHDLproject】/db/YSQ_8.fit.qmsg
S6【VHDLproject】/db/YSQ_8.hier_info
S6【VHDLproject】/db/YSQ_8.hif
S6【VHDLproject】/db/YSQ_8.ipinfo
S6【VHDLproject】/db/YSQ_8.lpc.html
S6【VHDLproject】/db/YSQ_8.lpc.rdb
S6【VHDLproject】/db/YSQ_8.lpc.txt
S6【VHDLproject】/db/YSQ_8.map.ammdb
S6【VHDLproject】/db/YSQ_8.map.bpm
S6【VHDLproject】/db/YSQ_8.map.cdb
S6【VHDLproject】/db/YSQ_8.map.hdb
S6【VHDLproject】/db/YSQ_8.map.kpt
S6【VHDLproject】/db/YSQ_8.map.logdb
S6【VHDLproject】/db/YSQ_8.map.qmsg
S6【VHDLproject】/db/YSQ_8.map.rdb
S6【VHDLproject】/db/YSQ_8.map_bb.cdb
S6【VHDLproject】/db/YSQ_8.map_bb.hdb
S6【VHDLproject】/db/YSQ_8.map_bb.logdb
S6【VHDLproject】/db/YSQ_8.pre_map.hdb
S6【VHDLproject】/db/YSQ_8.pti_db_list.ddb
S6【VHDLproject】/db/YSQ_8.root_partition.map.reg_db.cdb
S6【VHDLproject】/db/YSQ_8.routing.rdb
S6【VHDLproject】/db/YSQ_8.rtlv.hdb
S6【VHDLproject】/db/YSQ_8.rtlv_sg.cdb
S6【VHDLproject】/db/YSQ_8.rtlv_sg_swap.cdb
S6【VHDLproject】/db/YSQ_8.sgdiff.cdb
S6【VHDLproject】/db/YSQ_8.sgdiff.hdb
S6【VHDLproject】/db/YSQ_8.sld_design_entry.sci
S6【VHDLproject】/db/YSQ_8.sld_design_entry_dsc.sci
S6【VHDLproject】/db/YSQ_8.smart_action.txt
S6【VHDLproject】/db/YSQ_8.sta.qmsg
S6【VHDLproject】/db/YSQ_8.sta.rdb
S6【VHDLproject】/db/YSQ_8.sta_cmp.8_slow_1200mv_85c.tdb
S6【VHDLproject】/db/YSQ_8.syn_hier_info
S6【VHDLproject】/db/YSQ_8.tiscmp.fastest_slow_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.fastest_slow_1200mv_85c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.fast_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.slow_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.slow_1200mv_85c.ddb
S6【VHDLproject】/db/YSQ_8.tis_db_list.ddb
S6【VHDLproject】/db/YSQ_8.vpr.ammdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.db_info
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.ammdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.dfp
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.kpt
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.logdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.rcfdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.dpi
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.hb_info
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.sig
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.kpt
S6【VHDLproject】/incremental_db/README
S6【VHDLproject】/output_files/YSQ_8.asm.rpt
S6【VHDLproject】/output_files/YSQ_8.done
S6【VHDLproject】/output_files/YSQ_8.eda.rpt
S6【VHDLproject】/output_files/YSQ_8.fit.rpt
S6【VHDLproject】/output_files/YSQ_8.fit.smsg
S6【VHDLproject】/output_files/YSQ_8.fit.summary
S6【VHDLproject】/output_files/YSQ_8.flow.rpt
S6【VHDLproject】/output_files/YSQ_8.jdi
S6【VHDLproject】/output_files/YSQ_8.map.rpt
S6【VHDLproject】/output_files/YSQ_8.map.summary
S6【VHDLproject】/output_files/YSQ_8.pin
S6【VHDLproject】/output_files/YSQ_8.sof
S6【VHDLproject】/output_files/YSQ_8.sta.rpt
S6【VHDLproject】/output_files/YSQ_8.sta.summary
S6【VHDLproject】/Readme.txt
S6【VHDLproject】/S6原理图.PNG
S6【VHDLproject】/simulation/modelsim/YSQ_8.sft
S6【VHDLproject】/simulation/modelsim/YSQ_8.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8.vo
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_0c_slow.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_0c_vhd_slow.sdo
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_85c_slow.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_85c_vhd_slow.sdo
S6【VHDLproject】/simulation/modelsim
S6【VHDLproject】/ALU_8.vhd
S6【VHDLproject】/ALU_8.vhd.bak
S6【VHDLproject】/CPU_8.bsf
S6【VHDLproject】/CPU_8.vhd
S6【VHDLproject】/CPU_8.vhd.bak
S6【VHDLproject】/db/logic_util_heursitic.dat
S6【VHDLproject】/db/prev_cmp_YSQ_8.qmsg
S6【VHDLproject】/db/YSQ_8.(0).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(0).cnf.hdb
S6【VHDLproject】/db/YSQ_8.(1).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(1).cnf.hdb
S6【VHDLproject】/db/YSQ_8.(2).cnf.cdb
S6【VHDLproject】/db/YSQ_8.(2).cnf.hdb
S6【VHDLproject】/db/YSQ_8.asm.qmsg
S6【VHDLproject】/db/YSQ_8.asm.rdb
S6【VHDLproject】/db/YSQ_8.asm_labs.ddb
S6【VHDLproject】/db/YSQ_8.cbx.xml
S6【VHDLproject】/db/YSQ_8.cmp.bpm
S6【VHDLproject】/db/YSQ_8.cmp.cdb
S6【VHDLproject】/db/YSQ_8.cmp.hdb
S6【VHDLproject】/db/YSQ_8.cmp.idb
S6【VHDLproject】/db/YSQ_8.cmp.kpt
S6【VHDLproject】/db/YSQ_8.cmp.logdb
S6【VHDLproject】/db/YSQ_8.cmp.rdb
S6【VHDLproject】/db/YSQ_8.cmp_merge.kpt
S6【VHDLproject】/db/YSQ_8.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
S6【VHDLproject】/db/YSQ_8.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
S6【VHDLproject】/db/YSQ_8.db_info
S6【VHDLproject】/db/YSQ_8.eda.qmsg
S6【VHDLproject】/db/YSQ_8.fit.qmsg
S6【VHDLproject】/db/YSQ_8.hier_info
S6【VHDLproject】/db/YSQ_8.hif
S6【VHDLproject】/db/YSQ_8.ipinfo
S6【VHDLproject】/db/YSQ_8.lpc.html
S6【VHDLproject】/db/YSQ_8.lpc.rdb
S6【VHDLproject】/db/YSQ_8.lpc.txt
S6【VHDLproject】/db/YSQ_8.map.ammdb
S6【VHDLproject】/db/YSQ_8.map.bpm
S6【VHDLproject】/db/YSQ_8.map.cdb
S6【VHDLproject】/db/YSQ_8.map.hdb
S6【VHDLproject】/db/YSQ_8.map.kpt
S6【VHDLproject】/db/YSQ_8.map.logdb
S6【VHDLproject】/db/YSQ_8.map.qmsg
S6【VHDLproject】/db/YSQ_8.map.rdb
S6【VHDLproject】/db/YSQ_8.map_bb.cdb
S6【VHDLproject】/db/YSQ_8.map_bb.hdb
S6【VHDLproject】/db/YSQ_8.map_bb.logdb
S6【VHDLproject】/db/YSQ_8.pre_map.hdb
S6【VHDLproject】/db/YSQ_8.pti_db_list.ddb
S6【VHDLproject】/db/YSQ_8.root_partition.map.reg_db.cdb
S6【VHDLproject】/db/YSQ_8.routing.rdb
S6【VHDLproject】/db/YSQ_8.rtlv.hdb
S6【VHDLproject】/db/YSQ_8.rtlv_sg.cdb
S6【VHDLproject】/db/YSQ_8.rtlv_sg_swap.cdb
S6【VHDLproject】/db/YSQ_8.sgdiff.cdb
S6【VHDLproject】/db/YSQ_8.sgdiff.hdb
S6【VHDLproject】/db/YSQ_8.sld_design_entry.sci
S6【VHDLproject】/db/YSQ_8.sld_design_entry_dsc.sci
S6【VHDLproject】/db/YSQ_8.smart_action.txt
S6【VHDLproject】/db/YSQ_8.sta.qmsg
S6【VHDLproject】/db/YSQ_8.sta.rdb
S6【VHDLproject】/db/YSQ_8.sta_cmp.8_slow_1200mv_85c.tdb
S6【VHDLproject】/db/YSQ_8.syn_hier_info
S6【VHDLproject】/db/YSQ_8.tiscmp.fastest_slow_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.fastest_slow_1200mv_85c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.fast_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.slow_1200mv_0c.ddb
S6【VHDLproject】/db/YSQ_8.tiscmp.slow_1200mv_85c.ddb
S6【VHDLproject】/db/YSQ_8.tis_db_list.ddb
S6【VHDLproject】/db/YSQ_8.vpr.ammdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.db_info
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.ammdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.dfp
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.kpt
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.logdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.cmp.rcfdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.dpi
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.cdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.hb_info
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hbdb.sig
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.hdb
S6【VHDLproject】/incremental_db/compiled_partitions/YSQ_8.root_partition.map.kpt
S6【VHDLproject】/incremental_db/README
S6【VHDLproject】/output_files/YSQ_8.asm.rpt
S6【VHDLproject】/output_files/YSQ_8.done
S6【VHDLproject】/output_files/YSQ_8.eda.rpt
S6【VHDLproject】/output_files/YSQ_8.fit.rpt
S6【VHDLproject】/output_files/YSQ_8.fit.smsg
S6【VHDLproject】/output_files/YSQ_8.fit.summary
S6【VHDLproject】/output_files/YSQ_8.flow.rpt
S6【VHDLproject】/output_files/YSQ_8.jdi
S6【VHDLproject】/output_files/YSQ_8.map.rpt
S6【VHDLproject】/output_files/YSQ_8.map.summary
S6【VHDLproject】/output_files/YSQ_8.pin
S6【VHDLproject】/output_files/YSQ_8.sof
S6【VHDLproject】/output_files/YSQ_8.sta.rpt
S6【VHDLproject】/output_files/YSQ_8.sta.summary
S6【VHDLproject】/Readme.txt
S6【VHDLproject】/S6原理图.PNG
S6【VHDLproject】/simulation/modelsim/YSQ_8.sft
S6【VHDLproject】/simulation/modelsim/YSQ_8.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8.vo
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_0c_slow.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_0c_vhd_slow.sdo
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_85c_slow.vho
S6【VHDLproject】/simulation/modelsim/YSQ_8_8_1200mv_85c_vhd_slow.sdo
S6【VHDLproject】/simulation/modelsim
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