CDN加速镜像 | 设为首页 | 加入收藏夹
登陆 | 会员注册
当前位置： 首页 资源下载 源码下载 嵌入式/单片机编程 VHDL编程
收藏

文件名称:if_single

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-06-12
  • 文件大小：
    293.69kb
  • 已下载：
    0次
  • 提 供 者：
    一***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

所以从语法上讲，多if语句（if... if… if…）可以建模具有优先级的条件判断结构；而单if语句（if...else if…else if…）和case语句可用于建模不带优先级的条件判断。但是随着综合工具优化能力的不断增强，新型的综合工具大多时候会自动优化掉优先级结构，以减少芯片面积，提高时序性能。另外，条件结构的综合结果是否带有优先级不但取决于综合工具的类型和版本，还和目标器件或目标库有直接关系-Therefore, grammatically, and more if statement (if ... if ... if ...) can be modeled conditional structure having priority　while the single if statement (if ... else if ... else if ...) and case statements available in modeling without priority　uated. But with the ability to optimize the synthesis tool continuously enhance new integrated tool will automatically optimize away most of the time priority structure to reduce chip area and improve timing performance. In addition, the combined result condition structure with or without priority not only depend on the type and version of the synthesis tools, and also a target device or directly related to the target libraries
(系统自动生成,下载前可以参看下载内容)

下载文件列表

if_single/case/case1.v
if_single/case/PrecisionRTL/case.psp
if_single/case/PrecisionRTL/case_impl_1/case1.edf
if_single/case/PrecisionRTL/case_impl_1/case1.prf
if_single/case/PrecisionRTL/case_impl_1/case1.xdb
if_single/case/PrecisionRTL/case_impl_1/case1_area.rep
if_single/case/PrecisionRTL/case_impl_1/case1_con_rep.sdc
if_single/case/PrecisionRTL/case_impl_1/case1_rtl.ixdb
if_single/case/PrecisionRTL/case_impl_1/case1_tech_con_rep.sdc
if_single/case/PrecisionRTL/case_impl_1/case1_timing.rep
if_single/case/PrecisionRTL/case_impl_1/case_impl_1.psi
if_single/case/PrecisionRTL/case_impl_1/hdlAnalyze_verilogfile
if_single/case/PrecisionRTL/case_impl_1/precision.log
if_single/case/PrecisionRTL/case_impl_1/precision_rtl.sdc
if_single/case/PrecisionRTL/case_impl_1/precision_tech.sdc
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/.rtlc_compile
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/.top
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/autotop.conf
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/depend/TOPMODULE.list
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/emptymod.list
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/hier.list
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/incr_driver.log
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/INCR/incr_rtlc.log
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/legalmodmap.db
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/rtlc.args
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/rtlc_args1.file
if_single/case/PrecisionRTL/case_impl_1/rtlc.out/vmw.mem_contents
if_single/case/PrecisionRTL/case_impl_1/rtlc_libs/work/case1.mod
if_single/case/PrecisionRTL/case_impl_1/rtlc_libs/work/case1.mod.body
if_single/case/PrecisionRTL/case_impl_1/rtlc_libs/work/rtlc_version_info
if_single/case/PrecisionRTL/case_impl_1/unfolded_operators.txt
if_single/case/PrecisionRTL/case_RTL_schematic.bmp
if_single/case/PrecisionRTL/case_schematic.bmp
if_single/case/PrecisionRTL/Thumbs.db
if_single/case/SynplifyPro/case1.prd
if_single/case/SynplifyPro/case1.prj
if_single/case/SynplifyPro/case_rtl_view.bmp
if_single/case/SynplifyPro/case_tech_view.bmp
if_single/case/SynplifyPro/rev_2/AutoConstraint_case1.sdc
if_single/case/SynplifyPro/rev_2/case1.edn
if_single/case/SynplifyPro/rev_2/case1.fse
if_single/case/SynplifyPro/rev_2/case1.prf
if_single/case/SynplifyPro/rev_2/case1.srm
if_single/case/SynplifyPro/rev_2/case1.srr
if_single/case/SynplifyPro/rev_2/case1.srs
if_single/case/SynplifyPro/rev_2/case1.tlg
if_single/case/SynplifyPro/rev_2/generic.fse
if_single/case/SynplifyPro/rev_2/generic.srd
if_single/case/SynplifyPro/rev_2/syntmp/case1.msg
if_single/case/SynplifyPro/rev_2/syntmp/case1.plg
if_single/case/SynplifyPro/Thumbs.db
if_single/case/syntmp.msg
if_single/decode/case/case_decode.v
if_single/decode/case/decode_case.psp
if_single/decode/case/decode_case_impl_1/case_decode.edf
if_single/decode/case/decode_case_impl_1/case_decode.prf
if_single/decode/case/decode_case_impl_1/case_decode.xdb
if_single/decode/case/decode_case_impl_1/case_decode_area.rep
if_single/decode/case/decode_case_impl_1/case_decode_con_rep.sdc
if_single/decode/case/decode_case_impl_1/case_decode_rtl.ixdb
if_single/decode/case/decode_case_impl_1/case_decode_tech_con_rep.sdc
if_single/decode/case/decode_case_impl_1/case_decode_timing.rep
if_single/decode/case/decode_case_impl_1/decode_case_impl_1.psi
if_single/decode/case/decode_case_impl_1/hdlAnalyze_verilogfile
if_single/decode/case/decode_case_impl_1/precision.log
if_single/decode/case/decode_case_impl_1/precision_rtl.sdc
if_single/decode/case/decode_case_impl_1/precision_tech.sdc
if_single/decode/case/decode_case_impl_1/rtlc.out/.rtlc_compile
if_single/decode/case/decode_case_impl_1/rtlc.out/.top
if_single/decode/case/decode_case_impl_1/rtlc.out/autotop.conf
if_single/decode/case/decode_case_impl_1/rtlc.out/depend/TOPMODULE.list
if_single/decode/case/decode_case_impl_1/rtlc.out/INCR/emptymod.list
if_single/decode/case/decode_case_impl_1/rtlc.out/INCR/hier.list
if_single/decode/case/decode_case_impl_1/rtlc.out/INCR/incr_driver.log
if_single/decode/case/decode_case_impl_1/rtlc.out/INCR/incr_rtlc.log
if_single/decode/case/decode_case_impl_1/rtlc.out/legalmodmap.db
if_single/decode/case/decode_case_impl_1/rtlc.out/rtlc.args
if_single/decode/case/decode_case_impl_1/rtlc.out/rtlc_args1.file
if_single/decode/case/decode_case_impl_1/rtlc.out/vmw.mem_contents
if_single/decode/case/decode_case_impl_1/rtlc_libs/work/case_decode.mod
if_single/decode/case/decode_case_impl_1/rtlc_libs/work/case_decode.mod.body
if_single/decode/case/decode_case_impl_1/rtlc_libs/work/rtlc_version_info
if_single/decode/case/decode_case_impl_1/unfolded_operators.txt
if_single/decode/case/precision_RTL_schematic.bmp
if_single/decode/case/precision_schematic.bmp
if_single/decode/case/rev_1/AutoConstraint_case_decode.sdc
if_single/decode/case/rev_1/case_decode.edn
if_single/decode/case/rev_1/case_decode.fse
if_single/decode/case/rev_1/case_decode.prf
if_single/decode/case/rev_1/case_decode.srm
if_single/decode/case/rev_1/case_decode.srr
if_single/decode/case/rev_1/case_decode.srs
if_single/de

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 搜珍网是交换下载平台，只提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 本站已设置防盗链，请勿用迅雷、QQ旋风等下载软件下载资源，下载后用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或换浏览器；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*快速评论： 推荐 一般 有密码 和说明不符 不是源码或资料 文件不全 不能解压 纯粹是垃圾
*内　　容：
*验 证 码：
搜珍网 www.dssz.com