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文件名称:CPU_Design

  • 所属分类：
    Other systems
  • 标签属性：
    [HTML]
  • 上传时间：
    2016-06-25
  • 文件大小：
    1.86mb
  • 已下载：
    0次
  • 提 供 者：
  • 相关连接：
    无
  • 下载说明：
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基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

CPU_Design/
CPU_Design/ACC.bsf
CPU_Design/ACC.vhd
CPU_Design/ACC.vhd.bak
CPU_Design/ALU.bsf
CPU_Design/ALU.vhd
CPU_Design/ALU.vhd.bak
CPU_Design/BR.bsf
CPU_Design/BR.vhd
CPU_Design/BR.vhd.bak
CPU_Design/CAR.bsf
CPU_Design/CAR.vhd
CPU_Design/CAR.vhd.bak
CPU_Design/CBR.bsf
CPU_Design/CBR.vhd
CPU_Design/CBR.vhd.bak
CPU_Design/CPU.asm.rpt
CPU_Design/CPU.done
CPU_Design/CPU.fit.rpt
CPU_Design/CPU.fit.smsg
CPU_Design/CPU.fit.summary
CPU_Design/CPU.flow.rpt
CPU_Design/CPU.map.rpt
CPU_Design/CPU.map.summary
CPU_Design/CPU.pin
CPU_Design/CPU.pof
CPU_Design/CPU.qpf
CPU_Design/CPU.qsf
CPU_Design/CPU.qws
CPU_Design/CPU.sim.rpt
CPU_Design/CPU.sof
CPU_Design/CPU.tan.rpt
CPU_Design/CPU.tan.summary
CPU_Design/CPU_assignment_defaults.qdf
CPU_Design/CPU_test.bdf
CPU_Design/CPU_test.vwf
CPU_Design/db/
CPU_Design/db/altsyncram_74c1.tdf
CPU_Design/db/altsyncram_a3c1.tdf
CPU_Design/db/altsyncram_avb1.tdf
CPU_Design/db/altsyncram_js61.tdf
CPU_Design/db/altsyncram_jub1.tdf
CPU_Design/db/altsyncram_ovb1.tdf
CPU_Design/db/CPU.(0).cnf.cdb
CPU_Design/db/CPU.(0).cnf.hdb
CPU_Design/db/CPU.(1).cnf.cdb
CPU_Design/db/CPU.(1).cnf.hdb
CPU_Design/db/CPU.(10).cnf.cdb
CPU_Design/db/CPU.(10).cnf.hdb
CPU_Design/db/CPU.(11).cnf.cdb
CPU_Design/db/CPU.(11).cnf.hdb
CPU_Design/db/CPU.(12).cnf.cdb
CPU_Design/db/CPU.(12).cnf.hdb
CPU_Design/db/CPU.(13).cnf.cdb
CPU_Design/db/CPU.(13).cnf.hdb
CPU_Design/db/CPU.(14).cnf.cdb
CPU_Design/db/CPU.(14).cnf.hdb
CPU_Design/db/CPU.(15).cnf.cdb
CPU_Design/db/CPU.(15).cnf.hdb
CPU_Design/db/CPU.(16).cnf.cdb
CPU_Design/db/CPU.(16).cnf.hdb
CPU_Design/db/CPU.(17).cnf.cdb
CPU_Design/db/CPU.(17).cnf.hdb
CPU_Design/db/CPU.(18).cnf.cdb
CPU_Design/db/CPU.(18).cnf.hdb
CPU_Design/db/CPU.(19).cnf.cdb
CPU_Design/db/CPU.(19).cnf.hdb
CPU_Design/db/CPU.(2).cnf.cdb
CPU_Design/db/CPU.(2).cnf.hdb
CPU_Design/db/CPU.(20).cnf.cdb
CPU_Design/db/CPU.(20).cnf.hdb
CPU_Design/db/CPU.(21).cnf.cdb
CPU_Design/db/CPU.(21).cnf.hdb
CPU_Design/db/CPU.(22).cnf.cdb
CPU_Design/db/CPU.(22).cnf.hdb
CPU_Design/db/CPU.(3).cnf.cdb
CPU_Design/db/CPU.(3).cnf.hdb
CPU_Design/db/CPU.(4).cnf.cdb
CPU_Design/db/CPU.(4).cnf.hdb
CPU_Design/db/CPU.(5).cnf.cdb
CPU_Design/db/CPU.(5).cnf.hdb
CPU_Design/db/CPU.(6).cnf.cdb
CPU_Design/db/CPU.(6).cnf.hdb
CPU_Design/db/CPU.(7).cnf.cdb
CPU_Design/db/CPU.(7).cnf.hdb
CPU_Design/db/CPU.(8).cnf.cdb
CPU_Design/db/CPU.(8).cnf.hdb
CPU_Design/db/CPU.(9).cnf.cdb
CPU_Design/db/CPU.(9).cnf.hdb
CPU_Design/db/CPU.asm.qmsg
CPU_Design/db/CPU.asm.rdb
CPU_Design/db/CPU.asm_labs.ddb
CPU_Design/db/CPU.cbx.xml
CPU_Design/db/CPU.cmp.bpm
CPU_Design/db/CPU.cmp.cdb
CPU_Design/db/CPU.cmp.ecobp
CPU_Design/db/CPU.cmp.hdb
CPU_Design/db/CPU.cmp.kpt
CPU_Design/db/CPU.cmp.logdb
CPU_Design/db/CPU.cmp.rdb
CPU_Design/db/CPU.cmp.tdb
CPU_Design/db/CPU.cmp0.ddb
CPU_Design/db/CPU.cmp_merge.kpt
CPU_Design/db/CPU.db_info
CPU_Design/db/CPU.eco.cdb
CPU_Design/db/CPU.eds_overflow
CPU_Design/db/CPU.fit.qmsg
CPU_Design/db/CPU.fnsim.cdb
CPU_Design/db/CPU.fnsim.hdb
CPU_Design/db/CPU.fnsim.qmsg
CPU_Design/db/CPU.hier_info
CPU_Design/db/CPU.hif
CPU_Design/db/CPU.lpc.html
CPU_Design/db/CPU.lpc.rdb
CPU_Design/db/CPU.lpc.txt
CPU_Design/db/CPU.map.bpm
CPU_Design/db/CPU.map.cdb
CPU_Design/db/CPU.map.ecobp
CPU_Design/db/CPU.map.hdb
CPU_Design/db/CPU.map.kpt
CPU_Design/db/CPU.map.logdb
CPU_Design/db/CPU.map.qmsg
CPU_Design/db/CPU.map_bb.cdb
CPU_Design/db/CPU.map_bb.hdb
CPU_Design/db/CPU.map_bb.logdb
CPU_Design/db/CPU.pre_map.cdb
CPU_Design/db/CPU.pre_map.hdb
CPU_Design/db/CPU.rtlv.hdb
CPU_Design/db/CPU.rtlv_sg.cdb
CPU_Design/db/CPU.rtlv_sg_swap.cdb
CPU_Design/db/CPU.sgdiff.cdb
CPU_Design/db/CPU.sgdiff.hdb
CPU_Design/db/CPU.sim.cvwf
CPU_Design/db/CPU.sim.hdb
CPU_Design/db/CPU.sim.qmsg
CPU_Design/db/CPU.sim.rdb
CPU_Design/db/CPU.simfam
CPU_Design/db/CPU.sld_design_entry.sci
CPU_Design/db/CPU.sld_design_entry_dsc.sci
CPU_Design/db/CPU.smart_action.txt
CPU_Design/db/CPU.syn_hier_info
CPU_Design/db/CPU.tan.qmsg
CPU_Design/db/CPU.tis_db_list.ddb
CPU_Design/db/logic_util_heursitic.dat
CPU_Design/db/mult_b011.tdf
CPU_Design/db/mult_n9t.tdf
CPU_Design/db/mux_frc.tdf
CPU_Design/db/prev_cmp_CPU.asm.qmsg
CPU_Design/db/prev_cmp_CPU.fit.qmsg
CPU_Design/db/prev_cmp_CPU.map.qmsg
CPU_Design/db/prev_cmp_CPU.qmsg
CPU_Design/db/prev_cmp_CPU.sim.qmsg
CPU_Design/db/prev_cmp_CPU.tan.qmsg
CPU_Design/db/wed.wsf
CPU_Design/incremental_db/
CPU_Design/incremental_db/compiled_partitions/
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.cdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcfdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.cmp.re.rcfdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.map.cdb
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
CPU_Design/incremental_db/compiled_partitions/CPU.root_partition.map.hdb
CPU_Design/increm

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