文件名称:pro
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文件大小:3.09mb
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S10420背照式CCD verilog 状态机驱动代码-S10420 back-illuminated CCD verilog state machine driver code
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下载文件列表
pro/
pro/db/
pro/db/.cmp.kpt
pro/db/logic_util_heursitic.dat
pro/db/prev_cmp_test.qmsg
pro/db/test.(0).cnf.cdb
pro/db/test.(0).cnf.hdb
pro/db/test.asm.qmsg
pro/db/test.asm.rdb
pro/db/test.asm_labs.ddb
pro/db/test.cbx.xml
pro/db/test.cmp.bpm
pro/db/test.cmp.cdb
pro/db/test.cmp.hdb
pro/db/test.cmp.idb
pro/db/test.cmp.logdb
pro/db/test.cmp.rdb
pro/db/test.cmp_merge.kpt
pro/db/test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
pro/db/test.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
pro/db/test.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
pro/db/test.db_info
pro/db/test.eda.qmsg
pro/db/test.fit.qmsg
pro/db/test.hier_info
pro/db/test.hif
pro/db/test.ipinfo
pro/db/test.lpc.html
pro/db/test.lpc.rdb
pro/db/test.lpc.txt
pro/db/test.map.ammdb
pro/db/test.map.bpm
pro/db/test.map.cdb
pro/db/test.map.hdb
pro/db/test.map.kpt
pro/db/test.map.logdb
pro/db/test.map.qmsg
pro/db/test.map.rdb
pro/db/test.map_bb.cdb
pro/db/test.map_bb.hdb
pro/db/test.map_bb.logdb
pro/db/test.npp.qmsg
pro/db/test.pre_map.hdb
pro/db/test.pti_db_list.ddb
pro/db/test.root_partition.map.reg_db.cdb
pro/db/test.routing.rdb
pro/db/test.rtlv.hdb
pro/db/test.rtlv_sg.cdb
pro/db/test.rtlv_sg_swap.cdb
pro/db/test.sgate.nvd
pro/db/test.sgate_sm.nvd
pro/db/test.sgdiff.cdb
pro/db/test.sgdiff.hdb
pro/db/test.sld_design_entry.sci
pro/db/test.sld_design_entry_dsc.sci
pro/db/test.smart_action.txt
pro/db/test.sta.qmsg
pro/db/test.sta.rdb
pro/db/test.sta_cmp.8_slow_1200mv_85c.tdb
pro/db/test.tis_db_list.ddb
pro/db/test.tiscmp.fast_1200mv_0c.ddb
pro/db/test.tiscmp.fastest_slow_1200mv_0c.ddb
pro/db/test.tiscmp.fastest_slow_1200mv_85c.ddb
pro/db/test.tiscmp.slow_1200mv_0c.ddb
pro/db/test.tiscmp.slow_1200mv_85c.ddb
pro/db/test.tmw_info
pro/db/test.vpr.ammdb
pro/incremental_db/
pro/incremental_db/README
pro/incremental_db/compiled_partitions/
pro/incremental_db/compiled_partitions/test.db_info
pro/incremental_db/compiled_partitions/test.root_partition.cmp.ammdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.cdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.dfp
pro/incremental_db/compiled_partitions/test.root_partition.cmp.hdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.logdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.rcfdb
pro/incremental_db/compiled_partitions/test.root_partition.map.cdb
pro/incremental_db/compiled_partitions/test.root_partition.map.dpi
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.cdb
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.hb_info
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.hdb
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.sig
pro/incremental_db/compiled_partitions/test.root_partition.map.hdb
pro/incremental_db/compiled_partitions/test.root_partition.map.kpt
pro/output_files/
pro/output_files/test.asm.rpt
pro/output_files/test.done
pro/output_files/test.eda.rpt
pro/output_files/test.fit.rpt
pro/output_files/test.fit.smsg
pro/output_files/test.fit.summary
pro/output_files/test.flow.rpt
pro/output_files/test.jdi
pro/output_files/test.map.rpt
pro/output_files/test.map.summary
pro/output_files/test.pin
pro/output_files/test.sof
pro/output_files/test.sta.rpt
pro/output_files/test.sta.summary
pro/simulation/
pro/simulation/modelsim/
pro/simulation/modelsim/modelsim.ini
pro/simulation/modelsim/msim_transcript
pro/simulation/modelsim/rtl_work/
pro/simulation/modelsim/rtl_work/_info
pro/simulation/modelsim/rtl_work/_temp/
pro/simulation/modelsim/rtl_work/_vmake
pro/simulation/modelsim/rtl_work/test/
pro/simulation/modelsim/rtl_work/test/_primary.dat
pro/simulation/modelsim/rtl_work/test/_primary.dbs
pro/simulation/modelsim/rtl_work/test/_primary.vhd
pro/simulation/modelsim/rtl_work/test/verilog.prw
pro/simulation/modelsim/rtl_work/test/verilog.psm
pro/simulation/modelsim/rtl_work/test_tb/
pro/simulation/modelsim/rtl_work/test_tb/_primary.dat
pro/simulation/modelsim/rtl_work/test_tb/_primary.dbs
pro/simulation/modelsim/rtl_work/test_tb/_primary.vhd
pro/simulation/modelsim/rtl_work/test_tb/verilog.prw
pro/simulation/modelsim/rtl_work/test_tb/verilog.psm
pro/simulation/modelsim/test.sft
pro/simulation/modelsim/test.vo
pro/simulation/modelsim/test.vt
pro/simulation/modelsim/test_8_1200mv_0c_slow.vo
pro/simulation/modelsim/test_8_1200mv_0c_v_slow.sdo
pro/simulation/modelsim/test_8_1200mv_85c_slow.vo
pro/simulation/modelsim/test_8_1200mv_85c_v_slow.sdo
pro/simulation/modelsim/test_min_1200mv_0c_fast.vo
pro/simulation/modelsim/test_min_1200mv_0c_v_fast.sdo
pro/simulation/modelsim/test_modelsim.xrf
pro/simulation/modelsim/test_run_msim_rtl_verilog.do
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak1
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak10
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak11
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak2
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak3
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak4
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.b
pro/db/
pro/db/.cmp.kpt
pro/db/logic_util_heursitic.dat
pro/db/prev_cmp_test.qmsg
pro/db/test.(0).cnf.cdb
pro/db/test.(0).cnf.hdb
pro/db/test.asm.qmsg
pro/db/test.asm.rdb
pro/db/test.asm_labs.ddb
pro/db/test.cbx.xml
pro/db/test.cmp.bpm
pro/db/test.cmp.cdb
pro/db/test.cmp.hdb
pro/db/test.cmp.idb
pro/db/test.cmp.logdb
pro/db/test.cmp.rdb
pro/db/test.cmp_merge.kpt
pro/db/test.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
pro/db/test.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
pro/db/test.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
pro/db/test.db_info
pro/db/test.eda.qmsg
pro/db/test.fit.qmsg
pro/db/test.hier_info
pro/db/test.hif
pro/db/test.ipinfo
pro/db/test.lpc.html
pro/db/test.lpc.rdb
pro/db/test.lpc.txt
pro/db/test.map.ammdb
pro/db/test.map.bpm
pro/db/test.map.cdb
pro/db/test.map.hdb
pro/db/test.map.kpt
pro/db/test.map.logdb
pro/db/test.map.qmsg
pro/db/test.map.rdb
pro/db/test.map_bb.cdb
pro/db/test.map_bb.hdb
pro/db/test.map_bb.logdb
pro/db/test.npp.qmsg
pro/db/test.pre_map.hdb
pro/db/test.pti_db_list.ddb
pro/db/test.root_partition.map.reg_db.cdb
pro/db/test.routing.rdb
pro/db/test.rtlv.hdb
pro/db/test.rtlv_sg.cdb
pro/db/test.rtlv_sg_swap.cdb
pro/db/test.sgate.nvd
pro/db/test.sgate_sm.nvd
pro/db/test.sgdiff.cdb
pro/db/test.sgdiff.hdb
pro/db/test.sld_design_entry.sci
pro/db/test.sld_design_entry_dsc.sci
pro/db/test.smart_action.txt
pro/db/test.sta.qmsg
pro/db/test.sta.rdb
pro/db/test.sta_cmp.8_slow_1200mv_85c.tdb
pro/db/test.tis_db_list.ddb
pro/db/test.tiscmp.fast_1200mv_0c.ddb
pro/db/test.tiscmp.fastest_slow_1200mv_0c.ddb
pro/db/test.tiscmp.fastest_slow_1200mv_85c.ddb
pro/db/test.tiscmp.slow_1200mv_0c.ddb
pro/db/test.tiscmp.slow_1200mv_85c.ddb
pro/db/test.tmw_info
pro/db/test.vpr.ammdb
pro/incremental_db/
pro/incremental_db/README
pro/incremental_db/compiled_partitions/
pro/incremental_db/compiled_partitions/test.db_info
pro/incremental_db/compiled_partitions/test.root_partition.cmp.ammdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.cdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.dfp
pro/incremental_db/compiled_partitions/test.root_partition.cmp.hdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.logdb
pro/incremental_db/compiled_partitions/test.root_partition.cmp.rcfdb
pro/incremental_db/compiled_partitions/test.root_partition.map.cdb
pro/incremental_db/compiled_partitions/test.root_partition.map.dpi
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.cdb
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.hb_info
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.hdb
pro/incremental_db/compiled_partitions/test.root_partition.map.hbdb.sig
pro/incremental_db/compiled_partitions/test.root_partition.map.hdb
pro/incremental_db/compiled_partitions/test.root_partition.map.kpt
pro/output_files/
pro/output_files/test.asm.rpt
pro/output_files/test.done
pro/output_files/test.eda.rpt
pro/output_files/test.fit.rpt
pro/output_files/test.fit.smsg
pro/output_files/test.fit.summary
pro/output_files/test.flow.rpt
pro/output_files/test.jdi
pro/output_files/test.map.rpt
pro/output_files/test.map.summary
pro/output_files/test.pin
pro/output_files/test.sof
pro/output_files/test.sta.rpt
pro/output_files/test.sta.summary
pro/simulation/
pro/simulation/modelsim/
pro/simulation/modelsim/modelsim.ini
pro/simulation/modelsim/msim_transcript
pro/simulation/modelsim/rtl_work/
pro/simulation/modelsim/rtl_work/_info
pro/simulation/modelsim/rtl_work/_temp/
pro/simulation/modelsim/rtl_work/_vmake
pro/simulation/modelsim/rtl_work/test/
pro/simulation/modelsim/rtl_work/test/_primary.dat
pro/simulation/modelsim/rtl_work/test/_primary.dbs
pro/simulation/modelsim/rtl_work/test/_primary.vhd
pro/simulation/modelsim/rtl_work/test/verilog.prw
pro/simulation/modelsim/rtl_work/test/verilog.psm
pro/simulation/modelsim/rtl_work/test_tb/
pro/simulation/modelsim/rtl_work/test_tb/_primary.dat
pro/simulation/modelsim/rtl_work/test_tb/_primary.dbs
pro/simulation/modelsim/rtl_work/test_tb/_primary.vhd
pro/simulation/modelsim/rtl_work/test_tb/verilog.prw
pro/simulation/modelsim/rtl_work/test_tb/verilog.psm
pro/simulation/modelsim/test.sft
pro/simulation/modelsim/test.vo
pro/simulation/modelsim/test.vt
pro/simulation/modelsim/test_8_1200mv_0c_slow.vo
pro/simulation/modelsim/test_8_1200mv_0c_v_slow.sdo
pro/simulation/modelsim/test_8_1200mv_85c_slow.vo
pro/simulation/modelsim/test_8_1200mv_85c_v_slow.sdo
pro/simulation/modelsim/test_min_1200mv_0c_fast.vo
pro/simulation/modelsim/test_min_1200mv_0c_v_fast.sdo
pro/simulation/modelsim/test_modelsim.xrf
pro/simulation/modelsim/test_run_msim_rtl_verilog.do
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak1
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak10
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak11
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak2
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak3
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.bak4
pro/simulation/modelsim/test_run_msim_rtl_verilog.do.b
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