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src_book/13.14.15.coding/
src_book/13.14.15.coding/rtl/
src_book/13.14.15.coding/synth/
src_book/16.inference/
src_book/16.inference/rtl/
src_book/16.inference/synth/
src_book/16.inference/synth/netgen/
src_book/16.inference/synth/netgen/map/
src_book/16.inference/synth/netgen/synthesis/
src_book/17.mixed_verilog_vhdl/
src_book/17.mixed_verilog_vhdl/rtl/
src_book/17.mixed_verilog_vhdl/synth/
src_book/17.mixed_verilog_vhdl/synth/top.ptwx
src_book/18.verilog/
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src_book/20.21.clocking/
src_book/20.21.clocking/cores/
src_book/20.21.clocking/rtl/
src_book/20.21.clocking/synth/
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src_book/20.21.clocking/synth/planAhead_run_1/synth.data/wt/
src_book/22.cdc/
src_book/22.cdc/rtl/
src_book/22.cdc/synth/
src_book/23.synchronizers/
src_book/23.synchronizers/rtl/
src_book/23.synchronizers/synth/
src_book/25.counter/
src_book/25.counter/cores/
src_book/25.counter/rtl/
src_book/25.counter/synth/
src_book/25.counter/synth/iseconfig/
src_book/25.counter/synth/planAhead_run_1/
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src_book/25.counter/synth/planAhead_run_1/synth.data/wt/
src_book/25.counter/synth/_xmsgs/
src_book/25.counter/synth_lfsr/
src_book/26.signed/
src_book/26.signed/cores/
src_book/26.signed/rtl/
src_book/26.signed/synth/
src_book/26.signed/synth/netgen/
src_book/26.signed/synth/netgen/synthesis/
src_book/27.state_machines/
src_book/27.state_machines/rtl/
src_book/27.state_machines/synth/
src_book/28.dsp/
src_book/28.dsp/cores/
src_book/28.dsp/rtl/
src_book/28.dsp/synth/
src_book/29.reset/
src_book/29.reset/rtl/
src_book/29.reset/synth/
src_book/30.shift_regs/
src_book/30.shift_regs/cores/
src_book/30.shift_regs/rtl/
src_book/30.shift_regs/synth/
src_book/30.shift_regs/synth/planAhead_run_1/
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src_book/32.carry_chains/
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src_book/32.carry_chains/synth/
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src_book/32.carry_chains/synth/netgen/translate/
src_book/33.pipelines/
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src_book/33.pipelines/synth/
src_book/34.emb_memories/
src_book/34.emb_memories/cores/
src_book/34.emb_memories/rtl/
src_book/34.emb_memories/synth/
src_book/35.bitstream/
src_book/37.reconfiguration/
src_book/37.reconfiguration/rtl/
src_book/37.reconfiguration/synth/
src_book/37.reconfiguration/synth_pr/
src_book/37.reconfiguration/top_pr.bgn
src_book/38.area/
src_book/38.area/rtl/
src_book/38.area/synth/
src_book/38.area/synth/planAhead_run_1/
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src_book/38.area/synth/planAhead_run_1/synth.data/wt/
src_book/40.power_estimate/
src_book/40.power_estimate/mig_cores/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/example_top.pwr
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/par/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/par/compatible_ucf/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/controller/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/ecc/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/ip_top/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/phy/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/traffic_gen/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/rtl/ui/
src_book/40.power_estimate/mig_cores/mig_v3_4_high_freq/example_design/xpower1.bat
src_book/40.power_estimate/plan_ahead/
src_book/40.power_estimate/plan_ahead/mig_rtl/
src_book/40.power_estimate/plan_ahead/mig_rtl/mig_rtl.data/
src_book/40.power_estimate/plan_ahead/mig_rtl/mig_rtl.data/constrs_1/
src_book/40.power_estimate/plan_ahead/mig_rtl/mig_rtl.data/sources_1/
src_book/