文件名称:verilog
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本文档设计了1光栅位移传感器信号的接收、光栅位移传感器信号的整形及电平转换电路设计，用Verilog HDL描述了锁相倍频细分和零位信号处理电路。利用FPGA实现光栅位移系统与上位机接口的电路原理框图-This document designed a grating displacement sensor signal reception, grating displacement sensor signal shaping and level conversion circuit design, using Verilog HDL descr iption of segments and zero phase-locked harmonic signal processing circuit. Grating displacement system using FPGA and host computer interface circuit block diagram
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下载文件列表
verilog/aurora_8b10b_v8_3.v
verilog/aurora_8b10b_v8_3_aurora_lane_4byte.v
verilog/aurora_8b10b_v8_3_axi_to_ll.v
verilog/aurora_8b10b_v8_3_channel_err_detect.v
verilog/aurora_8b10b_v8_3_channel_init_sm.v
verilog/aurora_8b10b_v8_3_chbond_count_dec_4byte.v
verilog/aurora_8b10b_v8_3_clock_module.v
verilog/aurora_8b10b_v8_3_core.v
verilog/aurora_8b10b_v8_3_err_detect_4byte.v
verilog/aurora_8b10b_v8_3_global_logic.v
verilog/aurora_8b10b_v8_3_idle_and_ver_gen.v
verilog/aurora_8b10b_v8_3_lane_init_sm_4byte.v
verilog/aurora_8b10b_v8_3_left_align_control.v
verilog/aurora_8b10b_v8_3_left_align_mux.v
verilog/aurora_8b10b_v8_3_ll_to_axi.v
verilog/aurora_8b10b_v8_3_output_mux.v
verilog/aurora_8b10b_v8_3_output_switch_control.v
verilog/aurora_8b10b_v8_3_reset_logic.v
verilog/aurora_8b10b_v8_3_rx_ll.v
verilog/aurora_8b10b_v8_3_rx_ll_deframer.v
verilog/aurora_8b10b_v8_3_rx_ll_pdu_datapath.v
verilog/aurora_8b10b_v8_3_sideband_output.v
verilog/aurora_8b10b_v8_3_standard_cc_module.v
verilog/aurora_8b10b_v8_3_storage_ce_control.v
verilog/aurora_8b10b_v8_3_storage_count_control.v
verilog/aurora_8b10b_v8_3_storage_mux.v
verilog/aurora_8b10b_v8_3_storage_switch_control.v
verilog/aurora_8b10b_v8_3_sym_dec_4byte.v
verilog/aurora_8b10b_v8_3_sym_gen_4byte.v
verilog/aurora_8b10b_v8_3_tile.v
verilog/aurora_8b10b_v8_3_transceiver_wrapper.v
verilog/aurora_8b10b_v8_3_tx_ll.v
verilog/aurora_8b10b_v8_3_tx_ll_control.v
verilog/aurora_8b10b_v8_3_tx_ll_datapath.v
verilog/aurora_8b10b_v8_3_valid_data_counter.v
verilog/aurora_soc.v
verilog/fifo_generator_v9_3.v
verilog
verilog/aurora_8b10b_v8_3_aurora_lane_4byte.v
verilog/aurora_8b10b_v8_3_axi_to_ll.v
verilog/aurora_8b10b_v8_3_channel_err_detect.v
verilog/aurora_8b10b_v8_3_channel_init_sm.v
verilog/aurora_8b10b_v8_3_chbond_count_dec_4byte.v
verilog/aurora_8b10b_v8_3_clock_module.v
verilog/aurora_8b10b_v8_3_core.v
verilog/aurora_8b10b_v8_3_err_detect_4byte.v
verilog/aurora_8b10b_v8_3_global_logic.v
verilog/aurora_8b10b_v8_3_idle_and_ver_gen.v
verilog/aurora_8b10b_v8_3_lane_init_sm_4byte.v
verilog/aurora_8b10b_v8_3_left_align_control.v
verilog/aurora_8b10b_v8_3_left_align_mux.v
verilog/aurora_8b10b_v8_3_ll_to_axi.v
verilog/aurora_8b10b_v8_3_output_mux.v
verilog/aurora_8b10b_v8_3_output_switch_control.v
verilog/aurora_8b10b_v8_3_reset_logic.v
verilog/aurora_8b10b_v8_3_rx_ll.v
verilog/aurora_8b10b_v8_3_rx_ll_deframer.v
verilog/aurora_8b10b_v8_3_rx_ll_pdu_datapath.v
verilog/aurora_8b10b_v8_3_sideband_output.v
verilog/aurora_8b10b_v8_3_standard_cc_module.v
verilog/aurora_8b10b_v8_3_storage_ce_control.v
verilog/aurora_8b10b_v8_3_storage_count_control.v
verilog/aurora_8b10b_v8_3_storage_mux.v
verilog/aurora_8b10b_v8_3_storage_switch_control.v
verilog/aurora_8b10b_v8_3_sym_dec_4byte.v
verilog/aurora_8b10b_v8_3_sym_gen_4byte.v
verilog/aurora_8b10b_v8_3_tile.v
verilog/aurora_8b10b_v8_3_transceiver_wrapper.v
verilog/aurora_8b10b_v8_3_tx_ll.v
verilog/aurora_8b10b_v8_3_tx_ll_control.v
verilog/aurora_8b10b_v8_3_tx_ll_datapath.v
verilog/aurora_8b10b_v8_3_valid_data_counter.v
verilog/aurora_soc.v
verilog/fifo_generator_v9_3.v
verilog
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