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文件名称:UART_4

  • 所属分类：
    Other systems
  • 标签属性：
    [PDF]
  • 上传时间：
    2016-08-27
  • 文件大小：
    7.22mb
  • 已下载：
    0次
  • 提 供 者：
    木****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于verilog的串口程序,，能够实现接受发送和串并转换，-a uart program based on verilog,it can achieve the receive,send and serial/parallel conversion
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART_4/UART/.Xil/PlanAhead-2548-zhangchen-PC/ngc2edif/ngc2edif.log
UART_4/UART/.Xil/PlanAhead-2548-zhangchen-PC/ngc2edif/top.edif
UART_4/UART/.Xil/PlanAhead-2548-zhangchen-PC/ngc2edif/_xmsgs/ngc2edif.xmsgs
UART_4/UART/FIFO_GEN.v
UART_4/UART/fifo_test_1.fdo
UART_4/UART/fifo_test_1.udo
UART_4/UART/fifo_test_1.v
UART_4/UART/fifo_test_1_wave.fdo
UART_4/UART/fuse.log
UART_4/UART/fuse.xmsgs
UART_4/UART/fuseRelaunch.cmd
UART_4/UART/ipcore_dir/coregen.cgc
UART_4/UART/ipcore_dir/coregen.cgp
UART_4/UART/ipcore_dir/coregen.log
UART_4/UART/ipcore_dir/create_fifo.tcl
UART_4/UART/ipcore_dir/create_fifo1.tcl
UART_4/UART/ipcore_dir/create_fifo2.tcl
UART_4/UART/ipcore_dir/create_fifo_response_buffer.tcl
UART_4/UART/ipcore_dir/edit_fifo1.tcl
UART_4/UART/ipcore_dir/edit_fifo2.tcl
UART_4/UART/ipcore_dir/edit_fifo_response_buffer.tcl
UART_4/UART/ipcore_dir/fifo/doc/fifo_generator_v9_3_readme.txt
UART_4/UART/ipcore_dir/fifo/doc/fifo_generator_v9_3_vinfo.html
UART_4/UART/ipcore_dir/fifo/doc/pg057-fifo-generator.pdf
UART_4/UART/ipcore_dir/fifo/example_design/fifo_exdes.ucf
UART_4/UART/ipcore_dir/fifo/example_design/fifo_exdes.vhd
UART_4/UART/ipcore_dir/fifo/fifo_generator_v9_3_readme.txt
UART_4/UART/ipcore_dir/fifo/implement/implement.bat
UART_4/UART/ipcore_dir/fifo/implement/implement.sh
UART_4/UART/ipcore_dir/fifo/implement/implement_synplify.bat
UART_4/UART/ipcore_dir/fifo/implement/implement_synplify.sh
UART_4/UART/ipcore_dir/fifo/implement/planAhead_ise.bat
UART_4/UART/ipcore_dir/fifo/implement/planAhead_ise.sh
UART_4/UART/ipcore_dir/fifo/implement/planAhead_ise.tcl
UART_4/UART/ipcore_dir/fifo/implement/xst.prj
UART_4/UART/ipcore_dir/fifo/implement/xst.scr
UART_4/UART/ipcore_dir/fifo/simulation/fifo_dgen.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_dverif.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_pctrl.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_pkg.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_rng.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_synth.vhd
UART_4/UART/ipcore_dir/fifo/simulation/fifo_tb.vhd
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_isim.bat
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_isim.sh
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_mti.bat
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_mti.do
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_mti.sh
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_ncsim.bat
UART_4/UART/ipcore_dir/fifo/simulation/functional/simulate_vcs.bat
UART_4/UART/ipcore_dir/fifo/simulation/functional/ucli_commands.key
UART_4/UART/ipcore_dir/fifo/simulation/functional/vcs_session.tcl
UART_4/UART/ipcore_dir/fifo/simulation/functional/wave_isim.tcl
UART_4/UART/ipcore_dir/fifo/simulation/functional/wave_mti.do
UART_4/UART/ipcore_dir/fifo/simulation/functional/wave_ncsim.sv
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_isim.bat
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_isim.sh
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_mti.bat
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_mti.do
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_mti.sh
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_ncsim.bat
UART_4/UART/ipcore_dir/fifo/simulation/timing/simulate_vcs.bat
UART_4/UART/ipcore_dir/fifo/simulation/timing/ucli_commands.key
UART_4/UART/ipcore_dir/fifo/simulation/timing/vcs_session.tcl
UART_4/UART/ipcore_dir/fifo/simulation/timing/wave_isim.tcl
UART_4/UART/ipcore_dir/fifo/simulation/timing/wave_mti.do
UART_4/UART/ipcore_dir/fifo/simulation/timing/wave_ncsim.sv
UART_4/UART/ipcore_dir/fifo.asy
UART_4/UART/ipcore_dir/fifo.gise
UART_4/UART/ipcore_dir/fifo.ngc
UART_4/UART/ipcore_dir/fifo.sym
UART_4/UART/ipcore_dir/fifo.v
UART_4/UART/ipcore_dir/fifo.veo
UART_4/UART/ipcore_dir/fifo.xco
UART_4/UART/ipcore_dir/fifo.xise
UART_4/UART/ipcore_dir/fifo1/doc/fifo_generator_v9_3_readme.txt
UART_4/UART/ipcore_dir/fifo1/doc/fifo_generator_v9_3_vinfo.html
UART_4/UART/ipcore_dir/fifo1/doc/pg057-fifo-generator.pdf
UART_4/UART/ipcore_dir/fifo1/example_design/fifo1_exdes.ucf
UART_4/UART/ipcore_dir/fifo1/example_design/fifo1_exdes.vhd
UART_4/UART/ipcore_dir/fifo1/fifo_generator_v9_3_readme.txt
UART_4/UART/ipcore_dir/fifo1/implement/implement.bat
UART_4/UART/ipcore_dir/fifo1/implement/implement.sh
UART_4/UART/ipcore_dir/fifo1/implement/implement_synplify.bat
UART_4/UART/ipcore_dir/fifo1/implement/implement_synplify.sh
UART_4/UART/ipcore_dir/fifo1/implement/planAhead_ise.bat
UART_4/UART/ipcore_dir/fifo1/implement/planAhead_ise.sh
UART_4/UART/ipcore_dir/fifo1/implement/planAhead_ise.tcl
UART_4/UART/ipcore_dir/fifo1/implement/xst.prj
UART_4/UART/ipcore_dir/fifo1/implement/xst.scr
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_dgen.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_dverif.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_pctrl.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_pkg.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_rng.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_synth.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/fifo1_tb.vhd
UART_4/UART/ipcore_dir/fifo1/simulation/func

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