文件名称:pic10
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- 上传时间：2016-12-02
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本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。
tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务
其中有三篇文档：
PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好
PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考
PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test scr ipt code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test scr ipt file.
Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks
There are three documents:
PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well
PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference
PIC10F: PIC10 family of microcontrollers
tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务
其中有三篇文档：
PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写得非常好
PIC10F200_单片机IP核的实现.pdf:对上面的文章结合自己的实验过程进行了翻译和改写，给大家参考
PIC10F:PIC10系列单片机的手册-This folder inside the pic10 CPU is to achieve all the verilog code and the corresponding test scr ipt code, of course, there are some modules in quartus directly edit the waveform test, so there is no response to the test scr ipt file.
Tri_state_port test has not yet completed, test_pic10_status_reg.vt and test_pic10_tri_state_port2.vt are not complete test tasks
There are three documents:
PIC10_RISC_Design.pdf: the original (verilog code basically the original, on a part of the improvement), this article is written very well
PIC10F200_ IP core of the realization of single-chip.pdf: The above article combined with their own experimental process of translation and rewriting, for your reference
PIC10F: PIC10 family of microcontrollers
(系统自动生成,下载前可以参看下载内容)
下载文件列表
pic10_verilog/PIC10F.pdf
pic10_verilog/PIC10F200_单片机IP核的实现.pdf
pic10_verilog/pic10_alu.v
pic10_verilog/pic10_alu_datapath.v
pic10_verilog/pic10_alu_mux.v
pic10_verilog/pic10_controller.v
pic10_verilog/pic10_cpu.v
pic10_verilog/pic10_datapath.v
pic10_verilog/pic10_fsr.v
pic10_verilog/pic10_gpio_reg.v
pic10_verilog/pic10_ir.v
pic10_verilog/pic10_pc.v
pic10_verilog/pic10_pc_datapath.v
pic10_verilog/pic10_pc_mux.v
pic10_verilog/pic10_program_mux.v
pic10_verilog/pic10_program_store.v
pic10_verilog/pic10_ram_registers.v
pic10_verilog/pic10_ram_sfr_datapath.v
pic10_verilog/pic10_register_address_mux.v
pic10_verilog/PIC10_RISC_Design.pdf
pic10_verilog/pic10_sfr_data_mux.v
pic10_verilog/pic10_stack.v
pic10_verilog/pic10_status_reg.v
pic10_verilog/pic10_tris_reg.v
pic10_verilog/pic10_tri_state_port.v
pic10_verilog/pic10_w_reg.v
pic10_verilog/test_pic10_alu.vt
pic10_verilog/test_pic10_alu_datapath.vt
pic10_verilog/test_pic10_alu_mux.vt
pic10_verilog/test_pic10_cpu.vt
pic10_verilog/test_pic10_ir.vt
pic10_verilog/test_pic10_pc_datapath.vt
pic10_verilog/test_pic10_ram_registers.vt
pic10_verilog/test_pic10_ram_sfr_datapath.vt
pic10_verilog/test_pic10_stack.vt
pic10_verilog/test_pic10_status_reg.vt
pic10_verilog/test_pic10_tri_state_port.vt
pic10_verilog/test_pic10_tri_state_port2.vt
pic10_verilog/test_pic10_w_reg.vt
pic10_verilog
pic10_verilog/PIC10F200_单片机IP核的实现.pdf
pic10_verilog/pic10_alu.v
pic10_verilog/pic10_alu_datapath.v
pic10_verilog/pic10_alu_mux.v
pic10_verilog/pic10_controller.v
pic10_verilog/pic10_cpu.v
pic10_verilog/pic10_datapath.v
pic10_verilog/pic10_fsr.v
pic10_verilog/pic10_gpio_reg.v
pic10_verilog/pic10_ir.v
pic10_verilog/pic10_pc.v
pic10_verilog/pic10_pc_datapath.v
pic10_verilog/pic10_pc_mux.v
pic10_verilog/pic10_program_mux.v
pic10_verilog/pic10_program_store.v
pic10_verilog/pic10_ram_registers.v
pic10_verilog/pic10_ram_sfr_datapath.v
pic10_verilog/pic10_register_address_mux.v
pic10_verilog/PIC10_RISC_Design.pdf
pic10_verilog/pic10_sfr_data_mux.v
pic10_verilog/pic10_stack.v
pic10_verilog/pic10_status_reg.v
pic10_verilog/pic10_tris_reg.v
pic10_verilog/pic10_tri_state_port.v
pic10_verilog/pic10_w_reg.v
pic10_verilog/test_pic10_alu.vt
pic10_verilog/test_pic10_alu_datapath.vt
pic10_verilog/test_pic10_alu_mux.vt
pic10_verilog/test_pic10_cpu.vt
pic10_verilog/test_pic10_ir.vt
pic10_verilog/test_pic10_pc_datapath.vt
pic10_verilog/test_pic10_ram_registers.vt
pic10_verilog/test_pic10_ram_sfr_datapath.vt
pic10_verilog/test_pic10_stack.vt
pic10_verilog/test_pic10_status_reg.vt
pic10_verilog/test_pic10_tri_state_port.vt
pic10_verilog/test_pic10_tri_state_port2.vt
pic10_verilog/test_pic10_w_reg.vt
pic10_verilog
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