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文件名称:20161122_ff

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2016-12-27
  • 文件大小：
    319.25kb
  • 已下载：
    0次
  • 提 供 者：
    柳****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
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下载文件列表

20161122_ff/db/ff.(0).cnf.cdb
20161122_ff/db/ff.(0).cnf.hdb
20161122_ff/db/ff.cbx.xml
20161122_ff/db/ff.cmp.rdb
20161122_ff/db/ff.cmp_merge.kpt
20161122_ff/db/ff.db_info
20161122_ff/db/ff.eda.qmsg
20161122_ff/db/ff.hier_info
20161122_ff/db/ff.hif
20161122_ff/db/ff.lpc.html
20161122_ff/db/ff.lpc.rdb
20161122_ff/db/ff.lpc.txt
20161122_ff/db/ff.map.bpm
20161122_ff/db/ff.map.cdb
20161122_ff/db/ff.map.hdb
20161122_ff/db/ff.map.kpt
20161122_ff/db/ff.map.logdb
20161122_ff/db/ff.map.qmsg
20161122_ff/db/ff.map.rdb
20161122_ff/db/ff.map_bb.cdb
20161122_ff/db/ff.map_bb.hdb
20161122_ff/db/ff.map_bb.logdb
20161122_ff/db/ff.pre_map.cdb
20161122_ff/db/ff.pre_map.hdb
20161122_ff/db/ff.root_partition.map.reg_db.cdb
20161122_ff/db/ff.rtlv.hdb
20161122_ff/db/ff.rtlv_sg.cdb
20161122_ff/db/ff.rtlv_sg_swap.cdb
20161122_ff/db/ff.sgdiff.cdb
20161122_ff/db/ff.sgdiff.hdb
20161122_ff/db/ff.sld_design_entry.sci
20161122_ff/db/ff.sld_design_entry_dsc.sci
20161122_ff/db/ff.smart_action.txt
20161122_ff/db/ff.syn_hier_info
20161122_ff/db/ff.tis_db_list.ddb
20161122_ff/db/ff.tmw_info
20161122_ff/db/logic_util_heursitic.dat
20161122_ff/db/prev_cmp_ff.qmsg
20161122_ff/ff.done
20161122_ff/ff.eda.rpt
20161122_ff/ff.flow.rpt
20161122_ff/ff.map.rpt
20161122_ff/ff.map.summary
20161122_ff/ff.qpf
20161122_ff/ff.qsf
20161122_ff/ff.qws
20161122_ff/ff.v
20161122_ff/ff.v.bak
20161122_ff/ff_nativelink_simulation.rpt
20161122_ff/incremental_db/compiled_partitions/ff.db_info
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.cdb
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.dpi
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.hbdb.cdb
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.hbdb.hb_info
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.hbdb.hdb
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.hbdb.sig
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.hdb
20161122_ff/incremental_db/compiled_partitions/ff.root_partition.map.kpt
20161122_ff/incremental_db/README
20161122_ff/simulation/modelsim/ff.vt
20161122_ff/simulation/modelsim/ff.vt.bak
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak1
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak10
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak2
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak3
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak4
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak5
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak6
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak7
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak8
20161122_ff/simulation/modelsim/ff_run_msim_rtl_verilog.do.bak9
20161122_ff/simulation/modelsim/modelsim.ini
20161122_ff/simulation/modelsim/msim_transcript
20161122_ff/simulation/modelsim/rtl_work/ff/verilog.prw
20161122_ff/simulation/modelsim/rtl_work/ff/verilog.psm
20161122_ff/simulation/modelsim/rtl_work/ff/_primary.dat
20161122_ff/simulation/modelsim/rtl_work/ff/_primary.dbs
20161122_ff/simulation/modelsim/rtl_work/ff/_primary.vhd
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst/verilog.prw
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst/verilog.psm
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst/_primary.dat
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst/_primary.dbs
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst/_primary.vhd
20161122_ff/simulation/modelsim/rtl_work/_info
20161122_ff/simulation/modelsim/rtl_work/_vmake
20161122_ff/simulation/modelsim/vsim.wlf
20161122_ff/simulation/modelsim/rtl_work/ff
20161122_ff/simulation/modelsim/rtl_work/ff_vlg_tst
20161122_ff/simulation/modelsim/rtl_work/_temp
20161122_ff/simulation/modelsim/rtl_work
20161122_ff/incremental_db/compiled_partitions
20161122_ff/simulation/modelsim
20161122_ff/db
20161122_ff/incremental_db
20161122_ff/simulation
20161122_ff

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