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文件名称:ac97_verilog_sourcecode

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  • 上传时间:
    2008-10-13
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    122.45kb
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AC97芯片的verilog实现,有兴趣可以研究下。verilog是一种硬件开发语言,语法与c类似。与VHDL并列为IC开发两大编程语言
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ac97_ctrl/bench/CVS/Entries
ac97_ctrl/bench/CVS/Entries.Log
ac97_ctrl/bench/CVS/Repository
ac97_ctrl/bench/CVS/Root
ac97_ctrl/bench/CVS/Template
ac97_ctrl/bench/CVS
ac97_ctrl/bench/verilog/ac97_codec_sin.v
ac97_ctrl/bench/verilog/ac97_codec_sout.v
ac97_ctrl/bench/verilog/ac97_codec_top.v
ac97_ctrl/bench/verilog/CVS/Entries
ac97_ctrl/bench/verilog/CVS/Repository
ac97_ctrl/bench/verilog/CVS/Root
ac97_ctrl/bench/verilog/CVS/Template
ac97_ctrl/bench/verilog/CVS
ac97_ctrl/bench/verilog/tests.v
ac97_ctrl/bench/verilog/test_bench_top.v
ac97_ctrl/bench/verilog/wb_mast_model.v
ac97_ctrl/bench/verilog/wb_model_defines.v
ac97_ctrl/bench/verilog
ac97_ctrl/bench
ac97_ctrl/CVS/Entries
ac97_ctrl/CVS/Entries.Log
ac97_ctrl/CVS/Repository
ac97_ctrl/CVS/Root
ac97_ctrl/CVS/Template
ac97_ctrl/CVS
ac97_ctrl/doc/ac97_doc.pdf
ac97_ctrl/doc/CVS/Entries
ac97_ctrl/doc/CVS/Repository
ac97_ctrl/doc/CVS/Root
ac97_ctrl/doc/CVS/Template
ac97_ctrl/doc/CVS
ac97_ctrl/doc/README.txt
ac97_ctrl/doc/STATUS.txt
ac97_ctrl/doc
ac97_ctrl/rtl/CVS/Entries
ac97_ctrl/rtl/CVS/Entries.Log
ac97_ctrl/rtl/CVS/Repository
ac97_ctrl/rtl/CVS/Root
ac97_ctrl/rtl/CVS/Template
ac97_ctrl/rtl/CVS
ac97_ctrl/rtl/verilog/ac97_cra.v
ac97_ctrl/rtl/verilog/ac97_defines.v
ac97_ctrl/rtl/verilog/ac97_dma_if.v
ac97_ctrl/rtl/verilog/ac97_dma_req.v
ac97_ctrl/rtl/verilog/ac97_fifo_ctrl.v
ac97_ctrl/rtl/verilog/ac97_int.v
ac97_ctrl/rtl/verilog/ac97_in_fifo.v
ac97_ctrl/rtl/verilog/ac97_out_fifo.v
ac97_ctrl/rtl/verilog/ac97_prc.v
ac97_ctrl/rtl/verilog/ac97_rf.v
ac97_ctrl/rtl/verilog/ac97_rst.v
ac97_ctrl/rtl/verilog/ac97_sin.v
ac97_ctrl/rtl/verilog/ac97_soc.v
ac97_ctrl/rtl/verilog/ac97_sout.v
ac97_ctrl/rtl/verilog/ac97_top.v
ac97_ctrl/rtl/verilog/ac97_wb_if.v
ac97_ctrl/rtl/verilog/CVS/Entries
ac97_ctrl/rtl/verilog/CVS/Repository
ac97_ctrl/rtl/verilog/CVS/Root
ac97_ctrl/rtl/verilog/CVS/Template
ac97_ctrl/rtl/verilog/CVS
ac97_ctrl/rtl/verilog
ac97_ctrl/rtl
ac97_ctrl/sim/CVS/Entries
ac97_ctrl/sim/CVS/Entries.Log
ac97_ctrl/sim/CVS/Repository
ac97_ctrl/sim/CVS/Root
ac97_ctrl/sim/CVS/Template
ac97_ctrl/sim/CVS
ac97_ctrl/sim/rtl_sim/bin/CVS/Entries
ac97_ctrl/sim/rtl_sim/bin/CVS/Repository
ac97_ctrl/sim/rtl_sim/bin/CVS/Root
ac97_ctrl/sim/rtl_sim/bin/CVS/Template
ac97_ctrl/sim/rtl_sim/bin/CVS
ac97_ctrl/sim/rtl_sim/bin/Makefile
ac97_ctrl/sim/rtl_sim/bin
ac97_ctrl/sim/rtl_sim/CVS/Entries
ac97_ctrl/sim/rtl_sim/CVS/Entries.Log
ac97_ctrl/sim/rtl_sim/CVS/Repository
ac97_ctrl/sim/rtl_sim/CVS/Root
ac97_ctrl/sim/rtl_sim/CVS/Template
ac97_ctrl/sim/rtl_sim/CVS
ac97_ctrl/sim/rtl_sim/run/CVS/Entries
ac97_ctrl/sim/rtl_sim/run/CVS/Repository
ac97_ctrl/sim/rtl_sim/run/CVS/Root
ac97_ctrl/sim/rtl_sim/run/CVS/Template
ac97_ctrl/sim/rtl_sim/run/CVS
ac97_ctrl/sim/rtl_sim/run/Makefile
ac97_ctrl/sim/rtl_sim/run
ac97_ctrl/sim/rtl_sim
ac97_ctrl/sim
ac97_ctrl/syn/bin/comp.dc
ac97_ctrl/syn/bin/CVS/Entries
ac97_ctrl/syn/bin/CVS/Repository
ac97_ctrl/syn/bin/CVS/Root
ac97_ctrl/syn/bin/CVS/Template
ac97_ctrl/syn/bin/CVS
ac97_ctrl/syn/bin/design_spec.dc
ac97_ctrl/syn/bin/lib_spec.dc
ac97_ctrl/syn/bin/read.dc
ac97_ctrl/syn/bin
ac97_ctrl/syn/CVS/Entries
ac97_ctrl/syn/CVS/Entries.Log
ac97_ctrl/syn/CVS/Repository
ac97_ctrl/syn/CVS/Root
ac97_ctrl/syn/CVS/Template
ac97_ctrl/syn/CVS
ac97_ctrl/syn/log/CVS/Entries
ac97_ctrl/syn/log/CVS/Repository
ac97_ctrl/syn/log/CVS/Root
ac97_ctrl/syn/log/CVS/Template
ac97_ctrl/syn/log/CVS
ac97_ctrl/syn/log
ac97_ctrl/syn/out/CVS/Entries
ac97_ctrl/syn/out/CVS/Repository
ac97_ctrl/syn/out/CVS/Root
ac97_ctrl/syn/out/CVS/Template
ac97_ctrl/syn/out/CVS
ac97_ctrl/syn/out
ac97_ctrl/syn/run/CVS/Entries
ac97_ctrl/syn/run/CVS/Repository
ac97_ctrl/syn/run/CVS/Root
ac97_ctrl/syn/run/CVS/Template
ac97_ctrl/syn/run/CVS
ac97_ctrl/syn/run
ac97_ctrl/syn
ac97_ctrl
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