文件名称:sdram_16bit_latest.tar
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- 上传时间:2017-08-15
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这个IP核是一个小型的,简单的SDRAM控制器,用于为16位SDRAM芯片提供32位流水线的二叉树接口。
当访问开放行时,读写可以流水线实现完整的SDRAM总线利用率,但是读写之间的切换需要几个周期。(This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip.
When accessing open rows, reads and writes can be pipelined to achieve full SDRAM bus utilization, however switching between reads & writes takes a few cycles.
The row management strategy is to leave active rows open until a row needs to be closed for a periodic auto refresh or until that bank needs to open another row due to a read or write request.
This IP supports supports 4 open active rows (one per bank).)
当访问开放行时,读写可以流水线实现完整的SDRAM总线利用率,但是读写之间的切换需要几个周期。(This IP core is that of a small, simple SDRAM controller used to provide a 32-bit pipelined Wishbone interface to a 16-bit SDRAM chip.
When accessing open rows, reads and writes can be pipelined to achieve full SDRAM bus utilization, however switching between reads & writes takes a few cycles.
The row management strategy is to leave active rows open until a row needs to be closed for a periodic auto refresh or until that bank needs to open another row due to a read or write request.
This IP supports supports 4 open active rows (one per bank).)
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