spi\sim\run.do
spi\sim\vsim.wlf
spi\sim\work\spi_master\verilog.asm
spi\sim\work\spi_master\verilog.rw
spi\sim\work\spi_master\_primary.dat
spi\sim\work\spi_master\_primary.dbs
spi\sim\work\spi_master\_primary.vhd
spi\sim\work\spi_slave\verilog.asm
spi\sim\work\spi_slave\verilog.rw
spi\sim\work\spi_slave\_primary.dat
spi\sim\work\spi_slave\_primary.dbs
spi\sim\work\spi_slave\_primary.vhd
spi\sim\work\spi_test\verilog.asm
spi\sim\work\spi_test\verilog.rw
spi\sim\work\spi_test\_primary.dat
spi\sim\work\spi_test\_primary.dbs
spi\sim\work\spi_test\_primary.vhd
spi\sim\work\_info
spi\sim\work\_temp\vlog17gjsm
spi\sim\work\_temp\vlog1ibi6h
spi\sim\work\_temp\vlog1qbj9q
spi\sim\work\_temp\vlog2bzxzj
spi\sim\work\_temp\vlog34jiq2
spi\sim\work\_temp\vlog3xbdti
spi\sim\work\_temp\vlog46e1bs
spi\sim\work\_temp\vlog4zf2s4
spi\sim\work\_temp\vlog6e4iia
spi\sim\work\_temp\vlog6yzi2c
spi\sim\work\_temp\vlog6zt7y7
spi\sim\work\_temp\vlog740we6
spi\sim\work\_temp\vlog7k4wy4
spi\sim\work\_temp\vlog9ki8kf
spi\sim\work\_temp\vloga7a0r3
spi\sim\work\_temp\vlogb7g938
spi\sim\work\_temp\vlogcj56r8
spi\sim\work\_temp\vlogd5vgmn
spi\sim\work\_temp\vlogea7zh3
spi\sim\work\_temp\vlogen8ns7
spi\sim\work\_temp\vloggrznar
spi\sim\work\_temp\vlogk3nfek
spi\sim\work\_temp\vlogkatf1j
spi\sim\work\_temp\vlogm3na14
spi\sim\work\_temp\vlogm6hfdq
spi\sim\work\_temp\vlogmnmfxm
spi\sim\work\_temp\vlogrb1k9f
spi\sim\work\_temp\vlogri5kwd
spi\sim\work\_temp\vlogstnf2j
spi\sim\work\_temp\vlogvad30d
spi\sim\work\_temp\vlogw10jii
spi\sim\work\_temp\vlogw4y9kr
spi\sim\work\_temp\vlogwj5361
spi\sim\work\_temp\vlogwqxsn4
spi\sim\work\_temp\vlogyihb4y
spi\sim\work\_temp\vlogzy9i9x
spi\sim\work\_vmake
spi\sim\work.cr.mti
spi\sim\work.mpf
spi\src\spi_master.v
spi\src\spi_master.v.bak
spi\src\spi_slave.v
spi\src\spi_slave.v.bak
spi\src\spi_test.v
spi\src\spi_test.v.bak
spi\sim\work\spi_master
spi\sim\work\spi_slave
spi\sim\work\spi_test
spi\sim\work\_temp
spi\sim\work
spi\sim
spi\src
spi