文件名称:minirisc-master
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- 上传时间:2017-12-12
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文件大小:88kb
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Implementation of the MiniRisc CPU in Verilog!
相关搜索: risc
数字 Verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
文件名 | 大小 | 更新时间 |
---|---|---|
minirisc-master | ||
minirisc-master\README.txt | 4738 | 2017-12-04 |
minirisc-master\scode | ||
minirisc-master\scode\hex2v.c | 4001 | 2017-12-04 |
minirisc-master\scode\rf1.asm | 10096 | 2017-12-04 |
minirisc-master\scode\rf1.rom | 5248 | 2017-12-04 |
minirisc-master\scode\rf2.asm | 11685 | 2017-12-04 |
minirisc-master\scode\rf2.rom | 6472 | 2017-12-04 |
minirisc-master\scode\rf3.asm | 5472 | 2017-12-04 |
minirisc-master\scode\rf3.rom | 1963 | 2017-12-04 |
minirisc-master\scode\sanity1.asm | 4576 | 2017-12-04 |
minirisc-master\scode\sanity1.rom | 1621 | 2017-12-04 |
minirisc-master\scode\sanity2.asm | 6728 | 2017-12-04 |
minirisc-master\scode\sanity2.rom | 2530 | 2017-12-04 |
minirisc-master\scode\tmr_wdt.asm | 3167 | 2017-12-04 |
minirisc-master\scode\tmr_wdt.rom | 559 | 2017-12-04 |
minirisc-master\sim | ||
minirisc-master\sim\run | 467 | 2017-12-04 |
minirisc-master\verilog | ||
minirisc-master\verilog\core | ||
minirisc-master\verilog\core\alu.v | 5581 | 2017-12-04 |
minirisc-master\verilog\core\presclr_wdt.v | 4990 | 2017-12-04 |
minirisc-master\verilog\core\primitives.v | 5587 | 2017-12-04 |
minirisc-master\verilog\core\primitives_xilinx.v | 15710 | 2017-12-04 |
minirisc-master\verilog\core\register_file.v | 4535 | 2017-12-04 |
minirisc-master\verilog\core\risc_core.v | 23366 | 2017-12-04 |
minirisc-master\verilog\core\risc_core_top.v | 5608 | 2017-12-04 |
minirisc-master\verilog\testbench | ||
minirisc-master\verilog\testbench\prog_mem.v | 3366 | 2017-12-04 |
minirisc-master\verilog\testbench\test.v | 9320 | 2017-12-04 |
minirisc-master\xilinx_primitives.zip | 47060 | 2017-12-04 |
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