Floating　Point FP　multiplication　is　widely　used　in　large　set of scientific and signal　processing　computation.　Multiplication　is one of　the common　arithmetic operations　in　these　computations.　A　high　speed　floating　point　double　precision multiplier　is　implemented　on　a　Virtex 6 FPGA. In　addition, the　proposed　design　is compliant　with　IEEE 754　format　and　handles　over　flow,　under flow,　rounding　and various　exception　conditions. The　design　achieved　the　operating　frequency　of 414.714 MHz　with　an　area of　648　slices.