文件名称:y1
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- 上传时间：2018-04-03
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文件大小：20.95mb
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已下载：0次
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FPGA input clock frequency 50Mhz, try to design a frequency divider to realize 1Hz count signal. Requirements: writing design modules; Write the test model.
相关搜索： verilog hdl
(系统自动生成,下载前可以参看下载内容)
下载文件列表
| 文件名 | 大小 | 更新时间 |
|---|---|---|
| y1\db\logic_util_heursitic.dat | 6468 | 2018-04-02 |
| y1\db\prev_cmp_y1.qmsg | 55414 | 2018-04-02 |
| y1\db\y1.(0).cnf.cdb | 5642 | 2018-04-02 |
| y1\db\y1.(0).cnf.hdb | 1344 | 2018-04-02 |
| y1\db\y1.asm.qmsg | 2465 | 2018-04-02 |
| y1\db\y1.asm.rdb | 1396 | 2018-04-02 |
| y1\db\y1.asm_labs.ddb | 7788 | 2018-04-02 |
| y1\db\y1.cbx.xml | 84 | 2018-04-02 |
| y1\db\y1.cmp.bpm | 707 | 2018-04-02 |
| y1\db\y1.cmp.cdb | 16855 | 2018-04-02 |
| y1\db\y1.cmp.hdb | 13557 | 2018-04-02 |
| y1\db\y1.cmp.idb | 8485 | 2018-04-02 |
| y1\db\y1.cmp.kpt | 201 | 2018-04-02 |
| y1\db\y1.cmp.logdb | 13864 | 2018-04-02 |
| y1\db\y1.cmp.rdb | 21929 | 2018-04-02 |
| y1\db\y1.cmp_merge.kpt | 206 | 2018-04-02 |
| y1\db\y1.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd | 746342 | 2018-04-02 |
| y1\db\y1.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd | 745244 | 2018-04-02 |
| y1\db\y1.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd | 740377 | 2018-04-02 |
| y1\db\y1.db_info | 140 | 2018-04-02 |
| y1\db\y1.eda.qmsg | 5027 | 2018-04-02 |
| y1\db\y1.fit.qmsg | 20455 | 2018-04-02 |
| y1\db\y1.hier_info | 1985 | 2018-04-02 |
| y1\db\y1.hif | 451 | 2018-04-02 |
| y1\db\y1.ipinfo | 163 | 2018-04-02 |
| y1\db\y1.lpc.html | 372 | 2018-04-02 |
| y1\db\y1.lpc.rdb | 399 | 2018-04-02 |
| y1\db\y1.lpc.txt | 1060 | 2018-04-02 |
| y1\db\y1.map.ammdb | 123 | 2018-04-02 |
| y1\db\y1.map.bpm | 677 | 2018-04-02 |
| y1\db\y1.map.cdb | 6344 | 2018-04-02 |
| y1\db\y1.map.hdb | 12838 | 2018-04-02 |
| y1\db\y1.map.kpt | 1123 | 2018-04-02 |
| y1\db\y1.map.logdb | 4 | 2018-04-02 |
| y1\db\y1.map.qmsg | 7582 | 2018-04-02 |
| y1\db\y1.map.rdb | 1301 | 2018-04-02 |
| y1\db\y1.map_bb.cdb | 1838 | 2018-04-02 |
| y1\db\y1.map_bb.hdb | 9855 | 2018-04-02 |
| y1\db\y1.map_bb.logdb | 4 | 2018-04-02 |
| y1\db\y1.pplq.rdb | 232 | 2018-04-02 |
| y1\db\y1.pre_map.hdb | 11608 | 2018-04-02 |
| y1\db\y1.pti_db_list.ddb | 177 | 2018-04-02 |
| y1\db\y1.root_partition.map.reg_db.cdb | 193 | 2018-04-02 |
| y1\db\y1.routing.rdb | 4546 | 2018-04-02 |
| y1\db\y1.rtlv.hdb | 11562 | 2018-04-02 |
| y1\db\y1.rtlv_sg.cdb | 4685 | 2018-04-02 |
| y1\db\y1.rtlv_sg_swap.cdb | 181 | 2018-04-02 |
| y1\db\y1.sgdiff.cdb | 6176 | 2018-04-02 |
| y1\db\y1.sgdiff.hdb | 12153 | 2018-04-02 |
| y1\db\y1.sld_design_entry.sci | 202 | 2018-04-02 |
| y1\db\y1.sld_design_entry_dsc.sci | 202 | 2018-04-02 |
| y1\db\y1.smart_action.txt | 6 | 2018-04-02 |
| y1\db\y1.sta.qmsg | 17931 | 2018-04-02 |
| y1\db\y1.sta.rdb | 29936 | 2018-04-02 |
| y1\db\y1.sta_cmp.8_slow_1200mv_85c.tdb | 17104 | 2018-04-02 |
| y1\db\y1.syn_hier_info | 0 | 2018-04-02 |
| y1\db\y1.tiscmp.fastest_slow_1200mv_0c.ddb | 120304 | 2018-04-02 |
| y1\db\y1.tiscmp.fastest_slow_1200mv_85c.ddb | 120239 | 2018-04-02 |
| y1\db\y1.tiscmp.fast_1200mv_0c.ddb | 144805 | 2018-04-02 |
| y1\db\y1.tiscmp.slow_1200mv_0c.ddb | 145955 | 2018-04-02 |
| y1\db\y1.tiscmp.slow_1200mv_85c.ddb | 145656 | 2018-04-02 |
| y1\db\y1.tis_db_list.ddb | 235 | 2018-04-02 |
| y1\db\y1.tmw_info | 364 | 2018-04-02 |
| y1\db\y1.vpr.ammdb | 439 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.db_info | 140 | 2018-04-01 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.ammdb | 503 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.cdb | 8141 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.dfp | 33 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.hdb | 13217 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.kpt | 205 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.logdb | 4 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.cmp.rcfdb | 7539 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.cdb | 6304 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.dpi | 726 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.hbdb.cdb | 1289 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.hbdb.hb_info | 46 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.hbdb.hdb | 12527 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.hbdb.sig | 32 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.hdb | 12564 | 2018-04-02 |
| y1\incremental_db\compiled_partitions\y1.root_partition.map.kpt | 1108 | 2018-04-02 |
| y1\incremental_db\README | 653 | 2018-04-01 |
| y1\output_files\y1.asm.rpt | 6991 | 2018-04-02 |
| y1\output_files\y1.done | 26 | 2018-04-02 |
| y1\output_files\y1.eda.rpt | 7415 | 2018-04-02 |
| y1\output_files\y1.fit.rpt | 151457 | 2018-04-02 |
| y1\output_files\y1.fit.smsg | 703 | 2018-04-02 |
| y1\output_files\y1.fit.summary | 601 | 2018-04-02 |
| y1\output_files\y1.flow.rpt | 9555 | 2018-04-02 |
| y1\output_files\y1.jdi | 220 | 2018-04-02 |
| y1\output_files\y1.map.rpt | 23938 | 2018-04-02 |
| y1\output_files\y1.map.summary | 458 | 2018-04-02 |
| y1\output_files\y1.pin | 33031 | 2018-04-02 |
| y1\output_files\y1.sof | 358636 | 2018-04-02 |
| y1\output_files\y1.sta.rpt | 263317 | 2018-04-02 |
| y1\output_files\y1.sta.summary | 1713 | 2018-04-02 |
| y1\simulation\modelsim\modelsim.ini | 11131 | 2018-04-01 |
| y1\simulation\modelsim\msim_transcript | 1506 | 2018-04-01 |
| y1\simulation\modelsim\rtl_work\test\verilog.prw | 414 | 2018-04-01 |
| y1\simulation\modelsim\rtl_work\test\verilog.psm | 4936 | 2018-04-01 |
| y1\simulation\modelsim\rtl_work\test\_primary.dat | 493 | 2018-04-01 |
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