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文件名称:demodulation

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  • 上传时间:
    2018-08-26
  • 文件大小:
    128kb
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    3次
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基于verilog HDL的BPSK解调的FPGA实现,仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
(系统自动生成,下载前可以参看下载内容)

下载文件列表

project_2
project_2\.Xil
project_2\project_2.cache
project_2\project_2.cache\compile_simlib
project_2\project_2.cache\wt
project_2\project_2.cache\wt\synthesis.wdf
project_2\project_2.cache\wt\webtalk_pa.xml
project_2\project_2.cache\wt\xsim.wdf
project_2\project_2.sim
project_2\project_2.sim\sim_1
project_2\project_2.sim\sim_1\behav
project_2\project_2.sim\sim_1\behav\.Xil
project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-4824-Y3IPYJD01HWTT7R
project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-4824-Y3IPYJD01HWTT7R\webtalk
project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-5340-Y3IPYJD01HWTT7R
project_2\project_2.sim\sim_1\behav\.Xil\Webtalk-5340-Y3IPYJD01HWTT7R\webtalk
project_2\project_2.sim\sim_1\behav\compile.bat
project_2\project_2.sim\sim_1\behav\compile.log
project_2\project_2.sim\sim_1\behav\elaborate.bat
project_2\project_2.sim\sim_1\behav\elaborate.log
project_2\project_2.sim\sim_1\behav\glbl.v
project_2\project_2.sim\sim_1\behav\simulate.bat
project_2\project_2.sim\sim_1\behav\simulate.log
project_2\project_2.sim\sim_1\behav\test.tcl
project_2\project_2.sim\sim_1\behav\test_behav.wdb
project_2\project_2.sim\sim_1\behav\test_vlog.prj
project_2\project_2.sim\sim_1\behav\webtalk.jou
project_2\project_2.sim\sim_1\behav\webtalk.log
project_2\project_2.sim\sim_1\behav\webtalk_4824.backup.jou
project_2\project_2.sim\sim_1\behav\webtalk_4824.backup.log
project_2\project_2.sim\sim_1\behav\xelab.pb
project_2\project_2.sim\sim_1\behav\xsim.dir
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\Compile_Options.txt
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\webtalk
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\webtalk\.xsim_webtallk.info
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\webtalk\usage_statistics_ext_xsim.html
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\webtalk\usage_statistics_ext_xsim.xml
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.dbg
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.mem
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.reloc
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.rtti
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.svtype
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.type
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsim.xdbg
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsimcrash.log
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsimk.exe
project_2\project_2.sim\sim_1\behav\xsim.dir\test_behav\xsimkernel.log
project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib
project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\demodulation_dpsk.sdb
project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\glbl.sdb
project_2\project_2.sim\sim_1\behav\xsim.dir\xil_defaultlib\test.sdb
project_2\project_2.sim\sim_1\behav\xsim.dir\xsim.svtype
project_2\project_2.sim\sim_1\behav\xvlog.pb
project_2\project_2.srcs
project_2\project_2.srcs\sim_1
project_2\project_2.srcs\sim_1\new
project_2\project_2.srcs\sim_1\new\test.v
project_2\project_2.srcs\sources_1
project_2\project_2.srcs\sources_1\new
project_2\project_2.srcs\sources_1\new\demodulation_dpsk.v
project_2\project_2.xpr
project_2\vivado.jou
project_2\vivado.log
project_2\vivado_5292.backup.jou
project_2\vivado_5292.backup.log
project_2\vivado_5536.backup.jou
project_2\vivado_5536.backup.log
project_2\vivado_5632.backup.jou
project_2\vivado_5632.backup.log
project_2\vivado_5940.backup.jou
project_2\vivado_5940.backup.log
project_2\vivado_6208.backup.jou
project_2\vivado_6208.backup.log

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