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文件名称:cortex m0

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    2018-09-27
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    4.16mb
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产品号:AT510-MN-80001-r2p0-00rel0
ARM 官网最新M0 核
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : AT510-MN-80001-r2p0-00rel0.rar 列表
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/ARM_Cortex_M0_DesignStart_Eval_r2p0-00rel0_Release_Note.pdf
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/cores/cortexm0_designstart_r2p0/logical/cortexm0_integration/verilog/cortexm0ds_logic.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/cores/cortexm0_designstart_r2p0/logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/documentation/arm_cortex_m0_designstart_eval_fpga_user_guide.pdf
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/documentation/arm_cortex_m0_designstart_eval_user_guide.pdf
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_bitband/verilog/cmsdk_ahb_bitband.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/bin/BuildBusMatrix.pl
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/bin/lib/xmlparser.pm
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/README.txt
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_burst_arb.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_decode.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_default_slave.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_fixed_arb.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_input_stage.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_output_stage.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_round_arb.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_arb.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_bm_single_output_stage.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_lite.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/verilog/src/cmsdk_ahb_busmatrix_spirit.xml
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/xml/example2x3_full.xml
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_busmatrix/xml/example2x3_sparse.xml
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_downsizer64/verilog/cmsdk_ahb_downsizer64.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_eg_slave/verilog/cmsdk_ahb_eg_slave.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_eg_slave/verilog/cmsdk_ahb_eg_slave_interface.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_eg_slave/verilog/cmsdk_ahb_eg_slave_reg.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/bin/fm2conv.pl
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/example/frbm_example.fri
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/example/makefile
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/example/tbench.vc
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/example/tb_frbm_example.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_filereadcore.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_funnel.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master32.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_fileread_masters/verilog/cmsdk_ahb_fileread_master64.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_master_mux/verilog/cmsdk_ahb_master_mux.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_slave_mux/verilog/cmsdk_ahb_slave_mux.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_timeout_mon/verilog/cmsdk_ahb_timeout_mon.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_to_ahb_apb_async/verilog/cmsdk_ahb_to_ahb_apb_async.v
AT510-MN-80001-r2p0-00rel0/AT510-MN-80001-r2p0-00rel0/logical/cmsdk_ahb_to_ahb_apb_async/verilog/cmsdk_ahb_to_ahb

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