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文件名称:SPI接口Verilog实现

  • 所属分类：
    VHDL编程
  • 标签属性：
  • 上传时间：
    2021-04-22
  • 文件大小：
    4.33mb
  • 已下载：
    1次
  • 提 供 者：
    1091067664@qq.com
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

里面有主机发送模块和从机接收模块。主机发送32位16进制数（一位一位发送），工作在模式0。压缩文件内代码可直接运行，另附上testbench文件可以进行modelsim仿真。此代码根据论坛里一位大哥的代码改编，后来找不到是谁了。。。使用状态机编写主机的发送模块，由于项目仅仅需要主机发送所以从机的接收模块没有写成32位的，但是代码风格清晰，可以直接修改，复写率极高且非常好理解！
(系统自动生成,下载前可以参看下载内容)

下载文件列表

压缩包 : SPI3_SendToWeChat.rar 列表
SPI3/prj/db/.cmp.kpt
SPI3/prj/db/logic_util_heursitic.dat
SPI3/prj/db/prev_cmp_SPI_MasterToSlave.qmsg
SPI3/prj/db/SPI_MasterToSlave.(0).cnf.cdb
SPI3/prj/db/SPI_MasterToSlave.(0).cnf.hdb
SPI3/prj/db/SPI_MasterToSlave.(1).cnf.cdb
SPI3/prj/db/SPI_MasterToSlave.(1).cnf.hdb
SPI3/prj/db/SPI_MasterToSlave.asm.qmsg
SPI3/prj/db/SPI_MasterToSlave.asm.rdb
SPI3/prj/db/SPI_MasterToSlave.cbx.xml
SPI3/prj/db/SPI_MasterToSlave.cmp.idb
SPI3/prj/db/SPI_MasterToSlave.cmp.rdb
SPI3/prj/db/SPI_MasterToSlave.cmp_merge.kpt
SPI3/prj/db/SPI_MasterToSlave.db_info
SPI3/prj/db/SPI_MasterToSlave.eda.qmsg
SPI3/prj/db/SPI_MasterToSlave.fit.qmsg
SPI3/prj/db/SPI_MasterToSlave.hier_info
SPI3/prj/db/SPI_MasterToSlave.hif
SPI3/prj/db/SPI_MasterToSlave.ipinfo
SPI3/prj/db/SPI_MasterToSlave.lpc.html
SPI3/prj/db/SPI_MasterToSlave.lpc.rdb
SPI3/prj/db/SPI_MasterToSlave.lpc.txt
SPI3/prj/db/SPI_MasterToSlave.map.ammdb
SPI3/prj/db/SPI_MasterToSlave.map.bpm
SPI3/prj/db/SPI_MasterToSlave.map.cdb
SPI3/prj/db/SPI_MasterToSlave.map.hdb
SPI3/prj/db/SPI_MasterToSlave.map.kpt
SPI3/prj/db/SPI_MasterToSlave.map.logdb
SPI3/prj/db/SPI_MasterToSlave.map.qmsg
SPI3/prj/db/SPI_MasterToSlave.map.rdb
SPI3/prj/db/SPI_MasterToSlave.map_bb.cdb
SPI3/prj/db/SPI_MasterToSlave.map_bb.hdb
SPI3/prj/db/SPI_MasterToSlave.map_bb.logdb
SPI3/prj/db/SPI_MasterToSlave.pre_map.hdb
SPI3/prj/db/SPI_MasterToSlave.pti_db_list.ddb
SPI3/prj/db/SPI_MasterToSlave.root_partition.map.reg_db.cdb
SPI3/prj/db/SPI_MasterToSlave.routing.rdb
SPI3/prj/db/SPI_MasterToSlave.rtlv.hdb
SPI3/prj/db/SPI_MasterToSlave.rtlv_sg.cdb
SPI3/prj/db/SPI_MasterToSlave.rtlv_sg_swap.cdb
SPI3/prj/db/SPI_MasterToSlave.sgdiff.cdb
SPI3/prj/db/SPI_MasterToSlave.sgdiff.hdb
SPI3/prj/db/SPI_MasterToSlave.sld_design_entry.sci
SPI3/prj/db/SPI_MasterToSlave.sld_design_entry_dsc.sci
SPI3/prj/db/SPI_MasterToSlave.smart_action.txt
SPI3/prj/db/SPI_MasterToSlave.smp_dump.txt
SPI3/prj/db/SPI_MasterToSlave.sta.qmsg
SPI3/prj/db/SPI_MasterToSlave.sta.rdb
SPI3/prj/db/SPI_MasterToSlave.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd
SPI3/prj/db/SPI_MasterToSlave.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd
SPI3/prj/db/SPI_MasterToSlave.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd
SPI3/prj/db/SPI_MasterToSlave.tiscmp.fast_1200mv_0c.ddb
SPI3/prj/db/SPI_MasterToSlave.tiscmp.slow_1200mv_0c.ddb
SPI3/prj/db/SPI_MasterToSlave.tiscmp.slow_1200mv_85c.ddb
SPI3/prj/db/SPI_MasterToSlave.tis_db_list.ddb
SPI3/prj/db/SPI_MasterToSlave.vpr.ammdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.db_info
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.ammdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.cdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.dfp
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.hdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.logdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.cmp.rcfdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.cdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.dpi
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.hbdb.cdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.hbdb.hb_info
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.hbdb.hdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.hbdb.sig
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.hdb
SPI3/prj/incremental_db/compiled_partitions/SPI_MasterToSlave.root_partition.map.kpt
SPI3/prj/incremental_db/README
SPI3/prj/output_files/SPI_MasterToSlave.asm.rpt
SPI3/prj/output_files/SPI_MasterToSlave.done
SPI3/prj/output_files/SPI_MasterToSlave.eda.rpt
SPI3/prj/output_files/SPI_MasterToSlave.fit.rpt
SPI3/prj/output_files/SPI_MasterToSlave.fit.smsg
SPI3/prj/output_files/SPI_MasterToSlave.fit.summary
SPI3/prj/output_files/SPI_MasterToSlave.flow.rpt
SPI3/prj/output_files/SPI_MasterToSlave.jdi
SPI3/prj/output_files/SPI_MasterToSlave.map.rpt
SPI3/prj/output_files/SPI_MasterToSlave.map.smsg
SPI3/prj/output_files/SPI_MasterToSlave.map.summary
SPI3/prj/output_files/SPI_MasterToSlave.pin
SPI3/prj/output_files/SPI_MasterToSlave.sof
SPI3/prj/output_files/SPI_MasterToSlave.sta.rpt
SPI3/prj/output_files/SPI_MasterToSlave.sta.summary
SPI3/prj/simulation/modelsim/modelsim.ini
SPI3/prj/simulation/modelsim/msim_transcript
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave/verilog.prw
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave/verilog.psm
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave/_primary.dat
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave/_primary.dbs
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave/_primary.vhd
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave_tb/verilog.prw
SPI3/prj/simulation/modelsim/rtl_work/@s@p@i_@master@to@slave_tb/verilog.psm
SPI3/prj/simulatio

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