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文件名称:flowled

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  • 上传时间:
    2008-10-13
  • 文件大小:
    188.87kb
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    1次
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FPGA开发入门的Verilog HDL程序---流水灯,真实可用,验证通过,工程环境为Altera Quartus
(系统自动生成,下载前可以参看下载内容)

下载文件列表

flowled/db/add_sub_msh.tdf
flowled/db/flowled.(0).cnf.cdb
flowled/db/flowled.(0).cnf.hdb
flowled/db/flowled.analyze_file.qmsg
flowled/db/flowled.asm.qmsg
flowled/db/flowled.cbx.xml
flowled/db/flowled.cmp.cdb
flowled/db/flowled.cmp.hdb
flowled/db/flowled.cmp.kpt
flowled/db/flowled.cmp.logdb
flowled/db/flowled.cmp.rdb
flowled/db/flowled.cmp.tdb
flowled/db/flowled.cmp0.ddb
flowled/db/flowled.dbp
flowled/db/flowled.db_info
flowled/db/flowled.eco.cdb
flowled/db/flowled.eds_overflow
flowled/db/flowled.fit.qmsg
flowled/db/flowled.fnsim.hdb
flowled/db/flowled.fnsim.qmsg
flowled/db/flowled.hier_info
flowled/db/flowled.hif
flowled/db/flowled.map.cdb
flowled/db/flowled.map.hdb
flowled/db/flowled.map.logdb
flowled/db/flowled.map.qmsg
flowled/db/flowled.pre_map.cdb
flowled/db/flowled.pre_map.hdb
flowled/db/flowled.psp
flowled/db/flowled.rtlv.hdb
flowled/db/flowled.rtlv_sg.cdb
flowled/db/flowled.rtlv_sg_swap.cdb
flowled/db/flowled.sgdiff.cdb
flowled/db/flowled.sgdiff.hdb
flowled/db/flowled.signalprobe.cdb
flowled/db/flowled.sim.hdb
flowled/db/flowled.sim.qmsg
flowled/db/flowled.sim.rdb
flowled/db/flowled.sim_ori.vwf
flowled/db/flowled.sld_design_entry.sci
flowled/db/flowled.sld_design_entry_dsc.sci
flowled/db/flowled.syn_hier_info
flowled/db/flowled.tan.qmsg
flowled/db/wed.zsf
flowled/flowled.asm.rpt
flowled/flowled.cdf
flowled/flowled.done
flowled/flowled.dpf
flowled/flowled.fit.rpt
flowled/flowled.fit.smsg
flowled/flowled.fit.summary
flowled/flowled.flow.rpt
flowled/flowled.map
flowled/flowled.map.rpt
flowled/flowled.map.smsg
flowled/flowled.map.summary
flowled/flowled.pin
flowled/flowled.pof
flowled/flowled.qpf
flowled/flowled.qsf
flowled/flowled.qws
flowled/flowled.sim.rpt
flowled/flowled.sof
flowled/flowled.tan.rpt
flowled/flowled.tan.summary
flowled/flowled.v
flowled/flowled.vwf
flowled/output_file.map
flowled/db
flowled
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