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文件名称:基于fpga的多功能电子钟的设计

  • 所属分类：
    VHDL编程
  • 标签属性：
    [Text]
  • 上传时间：
    2012-09-04
  • 文件大小：
    339.59kb
  • 已下载：
    0次
  • 提 供 者：
    x****
  • 相关连接：
    无
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基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊,FPGA-based multi-functional electronic clock design to use would like to help everyone ah
相关搜索： vhdl 电子钟

(系统自动生成,下载前可以参看下载内容)

下载文件列表

200441123245276683
200441123245276683/100vhdl例子
200441123245276683/100vhdl例子/10_function
200441123245276683/100vhdl例子/10_function/10_bit_to_int.vhd
200441123245276683/100vhdl例子/10_function/README.TXT
200441123245276683/100vhdl例子/11_wiredor
200441123245276683/100vhdl例子/11_wiredor/11_wiredor.vhd
200441123245276683/100vhdl例子/11_wiredor/README.TXT
200441123245276683/100vhdl例子/12_convert
200441123245276683/100vhdl例子/12_convert/12_convert.vhd
200441123245276683/100vhdl例子/12_convert/README.TXT
200441123245276683/100vhdl例子/13_SHL
200441123245276683/100vhdl例子/13_SHL/13_SHL.VHD
200441123245276683/100vhdl例子/13_SHL/README.TXT
200441123245276683/100vhdl例子/14_MVL7_functions
200441123245276683/100vhdl例子/14_MVL7_functions/14_MVL7_functions.vhd
200441123245276683/100vhdl例子/14_MVL7_functions/README.TXT
200441123245276683/100vhdl例子/15_MUX41
200441123245276683/100vhdl例子/15_MUX41/15_MUX41.VHD
200441123245276683/100vhdl例子/15_MUX41/15_MVL7_functions.vhd
200441123245276683/100vhdl例子/15_MUX41/15_MVL7_syn_types.vhd
200441123245276683/100vhdl例子/15_MUX41/15_test_vectors_mux41.vhd
200441123245276683/100vhdl例子/15_MUX41/15_TYPES.VHD
200441123245276683/100vhdl例子/15_MUX41/README.TXT
200441123245276683/100vhdl例子/16_MUX
200441123245276683/100vhdl例子/16_MUX/16_multiple_mux.vhd
200441123245276683/100vhdl例子/16_MUX/16_MVL7_functions.vhd
200441123245276683/100vhdl例子/16_MUX/16_test_vectors.vhd
200441123245276683/100vhdl例子/16_MUX/16_TYPES.VHD
200441123245276683/100vhdl例子/16_MUX/README.TXT
200441123245276683/100vhdl例子/16_MUX/TYPES.VHD
200441123245276683/100vhdl例子/17_parity
200441123245276683/100vhdl例子/17_parity/17_parity.vhd
200441123245276683/100vhdl例子/17_parity/17_test_bench.vhd
200441123245276683/100vhdl例子/17_parity/README.TXT
200441123245276683/100vhdl例子/18_LIB
200441123245276683/100vhdl例子/18_LIB/18_tech_lib.vhd
200441123245276683/100vhdl例子/18_LIB/18_test_lib.vhd
200441123245276683/100vhdl例子/18_LIB/README.TXT
200441123245276683/100vhdl例子/19_test_194
200441123245276683/100vhdl例子/19_test_194/19_test_194.vhd
200441123245276683/100vhdl例子/1_ADDER
200441123245276683/100vhdl例子/1_ADDER/1_ADDER
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/1_ADDER.exp
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/files
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/files/L1.rpt
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/files/L2.rpt
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/files/L3.rpt
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/aa
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/aa/ADDER.sim
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/aa/ADDER.syn
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/aa/Anal.info
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/aa/Anal.out
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/WORK
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/WORK/Anal.info
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/WORK/Anal.out
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.sim
200441123245276683/100vhdl例子/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.syn
200441123245276683/100vhdl例子/1_ADDER/1_adder.acf
200441123245276683/100vhdl例子/1_ADDER/1_adder.hif
200441123245276683/100vhdl例子/1_ADDER/1_adder.mmf
200441123245276683/100vhdl例子/1_ADDER/1_ADDER.VHD
200441123245276683/100vhdl例子/1_ADDER/bir_rtl_adder.acf
200441123245276683/100vhdl例子/1_ADDER/bir_rtl_adder.hif
200441123245276683/100vhdl例子/1_ADDER/bir_rtl_adder.mmf
200441123245276683/100vhdl例子/1_ADDER/bir_rtl_adder.tdf
200441123245276683/100vhdl例子/1_ADDER/bit_rtl_adder.acf
200441123245276683/100vhdl例子/1_ADDER/bit_rtl_adder.hif
200441123245276683/100vhdl例子/1_ADDER/bit_rtl_adder.mmf
200441123245276683/100vhdl例子/1_ADDER/bit_rtl_adder.vhd
200441123245276683/100vhdl例子/1_ADDER/LIB.DLS
200441123245276683/100vhdl例子/1_ADDER/README.TXT
200441123245276683/100vhdl例子/1_ADDER/U2268397.DLS
200441123245276683/100vhdl例子/20_test_159
200441123245276683/100vhdl例子/20_test_159/20_test_159.vhd
200441123245276683/100vhdl例子/21_test_13a
200441123245276683/100vhdl例子/21_test_13a/21_test_13a.vhd
200441123245276683/100vhdl例子/22_deadlock
200441123245276683/100vhdl例子/22_deadlock/22_deadlock.vhd
200441123245276683/100vhdl例子/23_test_120
200441123245276683/100vhdl例子/23_test_120/23_Test_120.vhd
200441123245276683/100vhdl例子/24_test_195
200441123245276683/100vhdl例子/24_test_195/24_test_195.vhd
200441123245276683/100vhdl例子/25_test_1
200441123245276683/100vhdl例子/25_test_1/25_test_1.vhd
200441123245276683/100vhdl例子/25_test_1/25_test_1a.vhd
200441123245276683/100vhdl例子/26_test_74s
200441123245276683/100vhdl例子/26_test_74s/26_test_74s.vhd
200441123245276683/100vhdl例子/27_test_16
200441123245276683/100vhdl例子/27_test_16/27_test_16.vhd
200441123245276683/100vhdl例子/28_test_64a
200441123245276683/100vhdl例子/28_test_64a/28_Test_64a.vhd
200441123245276683/100vhdl例子/29_test_35
200441123245276683/100vhdl例子/29_test_35/29_Test_35.vhd
200441123245276683/100vhdl例子/2_ADDER
200441123245276683/100vhdl例子/2_ADDER/2_ADDER.VHD
200441123245276683/100vhdl例子/2_ADDER/README.TXT
200441123245276683/100vhdl例子/30_test_3
200441123245276683/100vhdl例子/30_test_3/30_Test_3.vhd

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