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文件名称:ddr_ddr2_sdram.rar

  • 所属分类：
    Embeded-SCM Develop
  • 标签属性：
    [MacOS]
  • 上传时间：
    2012-09-04
  • 文件大小：
    3.33mb
  • 已下载：
    0次
  • 提 供 者：
    Jac***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.,NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
相关搜索： ddr2 controller nios dd ddr2 ddr_ddr2_sdram nios d DDR2 vhdl ddr2 ni

(系统自动生成,下载前可以参看下载内容)

下载文件列表

ddr_ddr2_sdram/constraints/dat/ddr2_sdram_iotype.dat
ddr_ddr2_sdram/constraints/dat/ddr2_sdram_iotype_stratix.dat
ddr_ddr2_sdram/constraints/dat/ddr2_sdram_iotype_stratixii.dat
ddr_ddr2_sdram/constraints/dat/ddr_sdram_iotype.dat
ddr_ddr2_sdram/constraints/dat/ddr_sdram_iotype_stratix.dat
ddr_ddr2_sdram/constraints/dat/ddr_sdram_iotype_stratixii.dat
ddr_ddr2_sdram/constraints/dat/devices.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_f256_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_f256_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_f324_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_f324_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_q240_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c12_q240_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c20_f324_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c20_f324_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c20_f400_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c20_f400_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c3_t100_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c3_t100_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c3_t144_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c3_t144_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c4_f324_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c4_f324_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c4_f400_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c4_f400_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_f256_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_f256_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_q240_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_q240_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_t144_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1c6_t144_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_b672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_b672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f484_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f484_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f780_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s10_f780_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_b672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_b672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f484_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f484_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f780_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s20_f780_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_b672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_b672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f1020_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f1020_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f780_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s25_f780_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_b956_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_b956_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_f1020_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_f1020_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_f780_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s30_f780_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_b956_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_b956_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f1020_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f1020_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f1508_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f1508_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f780_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s40_f780_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_b956_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_b956_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_f1020_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_f1020_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_f1508_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s60_f1508_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_b956_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_b956_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_f1020_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_f1020_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_f1508_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1s80_f1508_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx10c_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx10c_f672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx10d_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx10d_f672_x8_v02.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx25c_f672_x8_floorplan_v00.dat
ddr_ddr2_sdram/constraints/dat/ep1sgx25c_f6

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