vga/automake.log
vga/coregen.log
vga/coregen.prj
vga/generic_dpram.v
vga/generic_spram.v
vga/prjname.lso
vga/sync_check.v
vga/tests.v
vga/tests.v.bak
vga/test_bench_top.v
vga/test_bench_top.v.bak
vga/timescale.v
vga/vga.dhp
vga/vga.npl
vga/vga_clkgen.v
vga/vga_colproc.v
vga/vga_csm_pb.v
vga/vga_curproc.v
vga/vga_cur_cregs.v
vga/vga_defines.v
vga/vga_defines.v.bak
vga/vga_enh_top.cmd_log
vga/vga_enh_top.lso
vga/vga_enh_top.prj
vga/vga_enh_top.stx
vga/vga_enh_top.syr
vga/vga_enh_top.v
vga/vga_enh_top_vhdl.prj
vga/vga_fifo.v
vga/vga_fifo_dc.v
vga/vga_pgen.v
vga/vga_tgen.v
vga/vga_vtim.v
vga/vga_wb_master.v
vga/vga_wb_master.v.bak
vga/vga_wb_slave.v
vga/vga_wb_slave.v.bak
vga/wb_b3_check.v
vga/wb_b3_check.v.bak
vga/wb_mast_model.v
vga/wb_model_defines.v
vga/wb_model_defines.v.bak
vga/wb_slv_model.v
vga/wb_slv_model.v.bak
vga/__projnav.log
vga/__projnav/coregen.rsp
vga/__projnav/runXst_tcl.rsp
vga/__projnav/vga.gfl
vga/__projnav/vga_enh_top.xst
vga/__projnav/vga_flowplus.gfl
vga/__projnav/xst_sprjTOstx_tcl.rsp
vga/xst/work/hdllib.ref
vga/xst/work/vlg7B/vga_tgen.bin
vga/xst/work/vlg6A/vga_enh_top.bin
vga/xst/work/vlg5F/vga_colproc.bin
vga/xst/work/vlg5D/vga_fifo.bin
vga/xst/work/vlg59/vga_clkgen.bin
vga/xst/work/vlg53/generic_spram.bin
vga/xst/work/vlg4D/vga_csm_pb.bin
vga/xst/work/vlg4D/vga_vtim.bin
vga/xst/work/vlg34/generic_dpram.bin
vga/xst/work/vlg07/vga_fifo_dc.bin
vga/xst/work/vlg07/vga_pgen.bin
vga/xst/work/vlg05/vga_wb_master.bin
vga/xst/work/vlg04/vga_wb_slave.bin
vga/xst/work/vlg7B
vga/xst/work/vlg6A
vga/xst/work/vlg5F
vga/xst/work/vlg5D
vga/xst/work/vlg59
vga/xst/work/vlg53
vga/xst/work/vlg4D
vga/xst/work/vlg34
vga/xst/work/vlg07
vga/xst/work/vlg05
vga/xst/work/vlg04
vga/xst/work
vga/__projnav
vga/xst
vga