LM3S系列ARM用GPIO模拟并行总线扩展32KB SRAM



PF0～PF7 D0～D7（数据总线）

PA0～PA7 A0～A7（地址总线低8位）

PB0～PB7 A8～A15（地址总线高8位）

PB7 /CE（片选）

PC4 /WE（写使能）

PC5 /OE（读使能）



32KB SRAM 映射在地址0x0000～0x4FFF之间

为了加快访问速度，软件上将采用寄存器方式进行操作

PB7原为/TRST功能，现在也解放出来作为地址线A15-ARM Series LM3S simulation using parallel bus GPIO expansion 32KB SRAM PF0 ~ PF7 D0 ~ D7 (Data Bus) PA0 ~ PA7 A0 ~ A7 (low address bus 8) PB0 ~ PB7 A8 ~ A15 (Address bus high 8 ) PB7/CE (chip select) PC4/WE (Write Enable) PC5/OE (read enable) 32KB SRAM mapped at address 0x0000 ~ 0x4FFF in order to speed up the access between the speed, the way software will be used to operate the register was PB7/TRST function, is also liberated as address line A15