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文件名称:Camera_Interface_Verilog

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [C/C++] [源码]
  • 上传时间：
    2012-10-31
  • 文件大小：
    339.89kb
  • 已下载：
    0次
  • 提 供 者：
    jin***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。-This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating C code, the sdc and ucf files for the FPGA synthiese, help document.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Camera_Interface_Verilog/bench/verilog/camera_bench_defines.v
Camera_Interface_Verilog/bench/verilog/camera_bench_top.v
Camera_Interface_Verilog/bench/verilog/wb_master32.v
Camera_Interface_Verilog/bench/verilog/wb_master_behavioral.v
Camera_Interface_Verilog/bench/verilog/wb_master_defines.v
Camera_Interface_Verilog/bench/verilog/wb_slave_behavioral.v
Camera_Interface_Verilog/doc/camera_specification.pdf
Camera_Interface_Verilog/rtl/verilog/camera_async_reset_flop.v
Camera_Interface_Verilog/rtl/verilog/camera_cb_table.v
Camera_Interface_Verilog/rtl/verilog/camera_cr_table.v
Camera_Interface_Verilog/rtl/verilog/camera_defines.v
Camera_Interface_Verilog/rtl/verilog/camera_fifo.v
Camera_Interface_Verilog/rtl/verilog/camera_fifo_ctrl.v
Camera_Interface_Verilog/rtl/verilog/camera_io_calc.v
Camera_Interface_Verilog/rtl/verilog/camera_synchronizer_flop.v
Camera_Interface_Verilog/rtl/verilog/camera_sync_ctrl.v
Camera_Interface_Verilog/rtl/verilog/camera_top.v
Camera_Interface_Verilog/rtl/verilog/camera_tpram.v
Camera_Interface_Verilog/rtl/verilog/camera_wb_if.v
Camera_Interface_Verilog/rtl/verilog/camera_y_table.v
Camera_Interface_Verilog/rtl/verilog/timescale.v
Camera_Interface_Verilog/sim/core_sw_simulator/b_cb.dat
Camera_Interface_Verilog/sim/core_sw_simulator/gen_yuv_rgb_files
Camera_Interface_Verilog/sim/core_sw_simulator/gen_yuv_rgb_files.c
Camera_Interface_Verilog/sim/core_sw_simulator/g_b_cb_case.dat
Camera_Interface_Verilog/sim/core_sw_simulator/g_cb.dat
Camera_Interface_Verilog/sim/core_sw_simulator/g_cr.dat
Camera_Interface_Verilog/sim/core_sw_simulator/rgb_out.dat
Camera_Interface_Verilog/sim/core_sw_simulator/rgb_scale_out.dat
Camera_Interface_Verilog/sim/core_sw_simulator/rgb_y.dat
Camera_Interface_Verilog/sim/core_sw_simulator/rgb_y_case.dat
Camera_Interface_Verilog/sim/core_sw_simulator/r_cr.dat
Camera_Interface_Verilog/sim/core_sw_simulator/r_g_cr_case.dat
Camera_Interface_Verilog/sim/core_sw_simulator/uyvy_in.dat
Camera_Interface_Verilog/sim/core_sw_simulator/yuv422_to_rgb
Camera_Interface_Verilog/sim/core_sw_simulator/yuv422_to_rgb.c
Camera_Interface_Verilog/sim/rtl_sim/bin/artisan_file_list.lst
Camera_Interface_Verilog/sim/rtl_sim/bin/cds.lib
Camera_Interface_Verilog/sim/rtl_sim/bin/hdl.var
Camera_Interface_Verilog/sim/rtl_sim/bin/ncelab.args
Camera_Interface_Verilog/sim/rtl_sim/bin/ncelab_xilinx.args
Camera_Interface_Verilog/sim/rtl_sim/bin/ncsim.rc
Camera_Interface_Verilog/sim/rtl_sim/bin/ncsim_waves.rc
Camera_Interface_Verilog/sim/rtl_sim/bin/rtl_file_list.lst
Camera_Interface_Verilog/sim/rtl_sim/bin/sim_file_list.lst
Camera_Interface_Verilog/sim/rtl_sim/bin/xilinx_file_list.lst
Camera_Interface_Verilog/sim/rtl_sim/log/ncelab_xilinx.log
Camera_Interface_Verilog/sim/rtl_sim/log/ncsim.log
Camera_Interface_Verilog/sim/rtl_sim/log/ncvlog.log
Camera_Interface_Verilog/sim/rtl_sim/run/clean
Camera_Interface_Verilog/sim/rtl_sim/run/ncsim.args
Camera_Interface_Verilog/sim/rtl_sim/run/ncsim.key
Camera_Interface_Verilog/sim/rtl_sim/run/ncvlog.args
Camera_Interface_Verilog/sim/rtl_sim/run/README.txt
Camera_Interface_Verilog/sim/rtl_sim/run/run_cam_sim_regr.scr
Camera_Interface_Verilog/sim/rtl_sim/run/top_groups.do
Camera_Interface_Verilog/syn/xilinx/constraints/camera.sdc
Camera_Interface_Verilog/syn/xilinx/constraints/camera.ucf
Camera_Interface_Verilog/sim/rtl_sim/bin/INCA_libs/worklib
Camera_Interface_Verilog/sim/rtl_sim/bin/INCA_libs
Camera_Interface_Verilog/sim/rtl_sim/bin
Camera_Interface_Verilog/sim/rtl_sim/log
Camera_Interface_Verilog/sim/rtl_sim/out
Camera_Interface_Verilog/sim/rtl_sim/run
Camera_Interface_Verilog/syn/xilinx/constraints
Camera_Interface_Verilog/bench/verilog
Camera_Interface_Verilog/rtl/verilog
Camera_Interface_Verilog/sim/core_sw_simulator
Camera_Interface_Verilog/sim/rtl_sim
Camera_Interface_Verilog/syn/xilinx
Camera_Interface_Verilog/bench
Camera_Interface_Verilog/doc
Camera_Interface_Verilog/rtl
Camera_Interface_Verilog/sim
Camera_Interface_Verilog/syn
Camera_Interface_Verilog

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