文件名称:viterbi_fpga
介绍说明--下载内容来自于网络,使用问题请自行百度
viterbi译码器的一种fpga实现.是一个cs252
的project的result
供大家研究用-Viterbi Decoder they simply a realization. Cs252 is a result of the project for all research
的project的result
供大家研究用-Viterbi Decoder they simply a realization. Cs252 is a result of the project for all research
(系统自动生成,下载前可以参看下载内容)
下载文件列表
viterbi_fpga/cs252/bak
viterbi_fpga/cs252/perl/altera_compatible.pl
viterbi_fpga/cs252/perl/change.pl
viterbi_fpga/cs252/perl/conf3
viterbi_fpga/cs252/perl/conf4
viterbi_fpga/cs252/perl/conf6
viterbi_fpga/cs252/perl/conf9
viterbi_fpga/cs252/perl/legible.pl
viterbi_fpga/cs252/perl/noise.pl
viterbi_fpga/cs252/perl/NOTES
viterbi_fpga/cs252/perl/viterbi.pl
viterbi_fpga/cs252/perl/viterbi_producer.pl
viterbi_fpga/cs252/perl
viterbi_fpga/cs252/results
viterbi_fpga/cs252/rtl/bak
viterbi_fpga/cs252/rtl/conf_3_4_2/acs1_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs1_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs2_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs2_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/backtrack.v
viterbi_fpga/cs252/rtl/conf_3_4_2/block.v
viterbi_fpga/cs252/rtl/conf_3_4_2/decoder.v
viterbi_fpga/cs252/rtl/conf_3_4_2/defs.h
viterbi_fpga/cs252/rtl/conf_3_4_2/in_signal.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/res_acs.v
viterbi_fpga/cs252/rtl/conf_3_4_2/res_stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/run
viterbi_fpga/cs252/rtl/conf_3_4_2/stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/tmp
viterbi_fpga/cs252/rtl/conf_3_4_2/top.v
viterbi_fpga/cs252/rtl/conf_3_4_2/verilog.log
viterbi_fpga/cs252/rtl/conf_3_4_2
viterbi_fpga/cs252/rtl/conf_3_8_8/acs1_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs1_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs2_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs2_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/backtrack.v
viterbi_fpga/cs252/rtl/conf_3_8_8/block.v
viterbi_fpga/cs252/rtl/conf_3_8_8/decoder.v
viterbi_fpga/cs252/rtl/conf_3_8_8/defs.h
viterbi_fpga/cs252/rtl/conf_3_8_8/in_signal.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/res_acs.v
viterbi_fpga/cs252/rtl/conf_3_8_8/res_stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/run
viterbi_fpga/cs252/rtl/conf_3_8_8/stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/tmp
viterbi_fpga/cs252/rtl/conf_3_8_8/top.v
viterbi_fpga/cs252/rtl/conf_3_8_8
viterbi_fpga/cs252/rtl/conf_4_12_6/acs1_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs1_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs2_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs2_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/backtrack.v
viterbi_fpga/cs252/rtl/conf_4_12_6/block.v
viterbi_fpga/cs252/rtl/conf_4_12_6/decoder.v
viterbi_fpga/cs252/rtl/conf_4_12_6/defs.h
viterbi_fpga/cs252/rtl/conf_4_12_6/in_signal.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/res_acs.v
viterbi_fpga/cs252/rtl/conf_4_12_6/res_stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/run
viterbi_fpga/cs252/rtl/conf_4_12_6/stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/tmp
viterbi_fpga/cs252/rtl/conf_4_12_6/top.v
viterbi_fpga/cs252/rtl/conf_4_12_6/verilog.log
viterbi_fpga/cs252/rtl/conf_4_12_6
viterbi_fpga/cs252/rtl/conf_4_20_1/acs1_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs1_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs2_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs2_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/backtrack.v
viterbi_fpga/cs252/rtl/conf_4_20_1/block.v
viterbi_fpga/cs252/rtl/conf_4_20_1/decoder.v
viterbi_fpga/cs252/rtl/conf_4_20_1/defs.h
viterbi_fpga/cs252/rtl/conf_4_20_1/in_signal.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/res_acs.v
viterbi_fpga/cs252/rtl/conf_4_20_1/res_stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/run
viterbi_fpga/cs252/rtl/conf_4_20_1/stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/tmp
viterbi_fpga/cs252/rtl/conf_4_20_1/top.v
viterbi_fpga/cs252/rtl/conf_4_20_1/verilog.log
viterbi_fpga/cs252/rtl/conf_4_20_1
viterbi_fpga/cs252/rtl/lib/acs1_0.v
viterbi_fpga/cs252/rtl/lib/acs1_1.v
viterbi_fpga/cs252/rtl/lib/acs2_0.v
viterbi_fpga/cs252/rtl/lib/acs2_1.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/lib/res_acs.v
viterbi_fpga/cs252/rtl/lib
viterbi_fpga/cs252/rtl/readme
viterbi_fpga/cs252/rtl/run
viterbi_fpga/cs252/rtl/TODO
viterbi_fpga/cs252/rtl
viterbi_fpga/cs252/新建文件夹
viterbi_fpga/cs252
viterbi_fpga
www.dssz.com.txt
viterbi_fpga/cs252/perl/altera_compatible.pl
viterbi_fpga/cs252/perl/change.pl
viterbi_fpga/cs252/perl/conf3
viterbi_fpga/cs252/perl/conf4
viterbi_fpga/cs252/perl/conf6
viterbi_fpga/cs252/perl/conf9
viterbi_fpga/cs252/perl/legible.pl
viterbi_fpga/cs252/perl/noise.pl
viterbi_fpga/cs252/perl/NOTES
viterbi_fpga/cs252/perl/viterbi.pl
viterbi_fpga/cs252/perl/viterbi_producer.pl
viterbi_fpga/cs252/perl
viterbi_fpga/cs252/results
viterbi_fpga/cs252/rtl/bak
viterbi_fpga/cs252/rtl/conf_3_4_2/acs1_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs1_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs2_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/acs2_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/backtrack.v
viterbi_fpga/cs252/rtl/conf_3_4_2/block.v
viterbi_fpga/cs252/rtl/conf_3_4_2/decoder.v
viterbi_fpga/cs252/rtl/conf_3_4_2/defs.h
viterbi_fpga/cs252/rtl/conf_3_4_2/in_signal.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_3_4_2/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/res_acs.v
viterbi_fpga/cs252/rtl/conf_3_4_2/res_stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/run
viterbi_fpga/cs252/rtl/conf_3_4_2/stage.v
viterbi_fpga/cs252/rtl/conf_3_4_2/tmp
viterbi_fpga/cs252/rtl/conf_3_4_2/top.v
viterbi_fpga/cs252/rtl/conf_3_4_2/verilog.log
viterbi_fpga/cs252/rtl/conf_3_4_2
viterbi_fpga/cs252/rtl/conf_3_8_8/acs1_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs1_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs2_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/acs2_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/backtrack.v
viterbi_fpga/cs252/rtl/conf_3_8_8/block.v
viterbi_fpga/cs252/rtl/conf_3_8_8/decoder.v
viterbi_fpga/cs252/rtl/conf_3_8_8/defs.h
viterbi_fpga/cs252/rtl/conf_3_8_8/in_signal.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_3_8_8/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/res_acs.v
viterbi_fpga/cs252/rtl/conf_3_8_8/res_stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/run
viterbi_fpga/cs252/rtl/conf_3_8_8/stage.v
viterbi_fpga/cs252/rtl/conf_3_8_8/tmp
viterbi_fpga/cs252/rtl/conf_3_8_8/top.v
viterbi_fpga/cs252/rtl/conf_3_8_8
viterbi_fpga/cs252/rtl/conf_4_12_6/acs1_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs1_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs2_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/acs2_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/backtrack.v
viterbi_fpga/cs252/rtl/conf_4_12_6/block.v
viterbi_fpga/cs252/rtl/conf_4_12_6/decoder.v
viterbi_fpga/cs252/rtl/conf_4_12_6/defs.h
viterbi_fpga/cs252/rtl/conf_4_12_6/in_signal.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_4_12_6/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/res_acs.v
viterbi_fpga/cs252/rtl/conf_4_12_6/res_stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/run
viterbi_fpga/cs252/rtl/conf_4_12_6/stage.v
viterbi_fpga/cs252/rtl/conf_4_12_6/tmp
viterbi_fpga/cs252/rtl/conf_4_12_6/top.v
viterbi_fpga/cs252/rtl/conf_4_12_6/verilog.log
viterbi_fpga/cs252/rtl/conf_4_12_6
viterbi_fpga/cs252/rtl/conf_4_20_1/acs1_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs1_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs2_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/acs2_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/backtrack.v
viterbi_fpga/cs252/rtl/conf_4_20_1/block.v
viterbi_fpga/cs252/rtl/conf_4_20_1/decoder.v
viterbi_fpga/cs252/rtl/conf_4_20_1/defs.h
viterbi_fpga/cs252/rtl/conf_4_20_1/in_signal.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/conf_4_20_1/MS_res_stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/res_acs.v
viterbi_fpga/cs252/rtl/conf_4_20_1/res_stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/run
viterbi_fpga/cs252/rtl/conf_4_20_1/stage.v
viterbi_fpga/cs252/rtl/conf_4_20_1/tmp
viterbi_fpga/cs252/rtl/conf_4_20_1/top.v
viterbi_fpga/cs252/rtl/conf_4_20_1/verilog.log
viterbi_fpga/cs252/rtl/conf_4_20_1
viterbi_fpga/cs252/rtl/lib/acs1_0.v
viterbi_fpga/cs252/rtl/lib/acs1_1.v
viterbi_fpga/cs252/rtl/lib/acs2_0.v
viterbi_fpga/cs252/rtl/lib/acs2_1.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS1_0.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS1_1.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS2_0.v
viterbi_fpga/cs252/rtl/lib/MS_res_ACS2_1.v
viterbi_fpga/cs252/rtl/lib/res_acs.v
viterbi_fpga/cs252/rtl/lib
viterbi_fpga/cs252/rtl/readme
viterbi_fpga/cs252/rtl/run
viterbi_fpga/cs252/rtl/TODO
viterbi_fpga/cs252/rtl
viterbi_fpga/cs252/新建文件夹
viterbi_fpga/cs252
viterbi_fpga
www.dssz.com.txt
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