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文件名称:freerisc8_11

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    2012-11-14
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    269.13kb
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一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Makefile
readme.txt
Verilog/
Verilog/alu.v
Verilog/basic.asm
Verilog/BASIC.HEX
Verilog/basic.rom
Verilog/cpu.v
Verilog/dds.asm
Verilog/DDS.HEX
Verilog/dds.rom
Verilog/dram.v
Verilog/exp.v
Verilog/hex2v
Verilog/hex2v.c
Verilog/idec.v
Verilog/pram.v
Verilog/regs.v
Verilog/runit
Verilog/sindata.c
Verilog/sindata.hex
Verilog/test.v
VHDL/
VHDL/ramlib_quartus.vhd
VHDL/ramlib_sim.vhd
VHDL/ramlib_xil.vhd
www/
www/freerisc8_legal.htm
www/images/
www/index.htm
www/risc8a.gif
www/risc8a_small.gif
www/risc8_manual.htm
www/_borders/
www/_borders/bottom.htm
www/_borders/_vti_cnf/
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www/_derived/
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